board/sbc8560/sbc8560.c

   1 /*
   2  * (C) Copyright 2003,Motorola Inc.
   3  * Xianghua Xiao, (X.Xiao@motorola.com)
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   8  * Added support for Wind River SBC8560 board
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29
  30 extern long int spd_sdram (void);
  31
  32 #include <common.h>
  33 #include <asm/processor.h>
  34 #include <asm/immap_85xx.h>
  35 #include <ioports.h>
  36 #include <spd.h>
  37 #include <miiphy.h>
  38
  39 long int fixed_sdram (void);
  40
  41 /*
  42  * I/O Port configuration table
  43  *
  44  * if conf is 1, then that port pin will be configured at boot time
  45  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  46  */
  47
  48 const iop_conf_t iop_conf_tab[4][32] = {
  49
  50     /* Port A configuration */
  51     {   /*            conf ppar psor pdir podr pdat */
  52         /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  53         /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  54         /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  55         /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  56         /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  57         /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  58         /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  59         /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  60         /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  61         /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  62         /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  63         /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  64         /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  65         /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  66         /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  67         /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  68         /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  69         /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  70         /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  71         /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  72         /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  73         /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  74         /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  75         /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  76         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  77         /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  78         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  79         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  80         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  81         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  82         /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  83         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  84     },
  85
  86     /* Port B configuration */
  87     {   /*            conf ppar psor pdir podr pdat */
  88         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  89         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  90         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  91         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  92         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  93         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  94         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  95         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  96         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  97         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  98         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
  99         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 100         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 101         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 102         /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 103         /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 104         /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 105         /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 106         /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 107         /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 108         /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 109         /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 110         /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 111         /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 112         /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 113         /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 114         /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 115         /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 116         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 117         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 118         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 119         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 120     },
 121
 122     /* Port C */
 123     {   /*            conf ppar psor pdir podr pdat */
 124         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 125         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 126         /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 127         /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 128         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 129         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 130         /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 131         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 132         /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 133         /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 134         /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 135         /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 136         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 137         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 138         /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 139         /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 140         /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 141         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 142         /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 143         /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 144         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 145         /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 146         /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 147         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 148         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 149         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 150         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 151         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 152         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 153         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 154         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 155         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 156     },
 157
 158     /* Port D */
 159     {   /*            conf ppar psor pdir podr pdat */
 160         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 161         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 162         /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
 163         /* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
 164         /* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
 165         /* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
 166         /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 167         /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 168         /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 169         /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 170         /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 171         /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 172         /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 173         /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 174         /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 175         /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 176         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 177         /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 178         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 179         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 180         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 181         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 182         /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 183         /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 184         /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 185         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 186         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 187         /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 188         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 189         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 190         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 191         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 192     }
 193 };
 194
 195 int board_early_init_f (void)
 196 {
 197 #if defined(CONFIG_PCI)
 198     volatile immap_t *immr = (immap_t *)CFG_IMMR;
 199     volatile ccsr_pcix_t *pci = &immr->im_pcix;
 200
 201     pci->peer &= 0xfffffffdf; /* disable master abort */
 202 #endif
 203         return 0;
 204 }
 205
 206 void reset_phy (void)
 207 {
 208 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
 209         volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
 210 #endif
 211         /* reset Giga bit Ethernet port if needed here */
 212
 213         /* reset the CPM FEC port */
 214 #if (CONFIG_ETHER_INDEX == 2)
 215         bcsr[0] &= ~0x20;
 216         udelay(2);
 217         bcsr[0] |= 0x20;
 218         udelay(1000);
 219 #elif (CONFIG_ETHER_INDEX == 3)
 220         bcsr[0] &= ~0x10;
 221         udelay(2);
 222         bcsr[0] |= 0x10;
 223         udelay(1000);
 224 #endif
 225 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
 226         /* reset PHY */
 227         miiphy_reset("FCC1 ETHERNET", 0x0);
 228
 229         /* change PHY address to 0x02 */
 230         bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
 231
 232         bb_miiphy_write(NULL, 0x02, PHY_BMCR,
 233                         PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 234 #endif /* CONFIG_MII */
 235 }
 236
 237 int checkboard (void)
 238 {
 239         sys_info_t sysinfo;
 240
 241         get_sys_info (&sysinfo);
 242
 243 #ifdef CONFIG_SBC8560
 244         printf ("Board: Wind River SBC8560 Board\n");
 245 #else
 246         printf ("Board: Wind River SBC8540 Board\n");
 247 #endif
 248         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 249         printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
 250         printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
 251         if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
 252                 || (CFG_LBC_LCRR & 0x0f) == 8) {
 253                 printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
 254         } else {
 255                 printf("\tLBC: unknown\n");
 256         }
 257         printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
 258         printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
 259         return (0);
 260 }
 261
 262
 263 long int initdram (int board_type)
 264 {
 265         long dram_size = 0;
 266         extern long spd_sdram (void);
 267         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 268 #if 0
 269 #if !defined(CONFIG_RAM_AS_FLASH)
 270         volatile ccsr_lbc_t *lbc= &immap->im_lbc;
 271         sys_info_t sysinfo;
 272         uint temp_lbcdll = 0;
 273 #endif
 274 #endif /* 0 */
 275 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
 276         volatile ccsr_gur_t *gur= &immap->im_gur;
 277 #endif
 278 #if defined(CONFIG_DDR_DLL)
 279         uint temp_ddrdll = 0;
 280
 281         /* Work around to stabilize DDR DLL */
 282         temp_ddrdll = gur->ddrdllcr;
 283         gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
 284         asm("sync;isync;msync");
 285 #endif
 286
 287 #if defined(CONFIG_SPD_EEPROM)
 288         dram_size = spd_sdram ();
 289 #else
 290         dram_size = fixed_sdram ();
 291 #endif
 292
 293 #if 0
 294 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
 295         get_sys_info(&sysinfo);
 296         /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
 297         if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
 298                 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
 299         } else {
 300 #if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
 301                 lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
 302 #endif
 303                 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
 304                 udelay(200);
 305                 temp_lbcdll = gur->lbcdllcr;
 306                 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 307                 asm("sync;isync;msync");
 308         }
 309         lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
 310         lbc->br2 = CFG_BR2_PRELIM;
 311         lbc->lbcr = CFG_LBC_LBCR;
 312         lbc->lsdmr = CFG_LBC_LSDMR_1;
 313         asm("sync");
 314         (unsigned int) * (ulong *)0 = 0x000000ff;
 315         lbc->lsdmr = CFG_LBC_LSDMR_2;
 316         asm("sync");
 317         (unsigned int) * (ulong *)0 = 0x000000ff;
 318         lbc->lsdmr = CFG_LBC_LSDMR_3;
 319         asm("sync");
 320         (unsigned int) * (ulong *)0 = 0x000000ff;
 321         lbc->lsdmr = CFG_LBC_LSDMR_4;
 322         asm("sync");
 323         (unsigned int) * (ulong *)0 = 0x000000ff;
 324         lbc->lsdmr = CFG_LBC_LSDMR_5;
 325         asm("sync");
 326         lbc->lsrt = CFG_LBC_LSRT;
 327         asm("sync");
 328         lbc->mrtpr = CFG_LBC_MRTPR;
 329         asm("sync");
 330 #endif
 331 #endif
 332
 333 #if defined(CONFIG_DDR_ECC)
 334         {
 335                 /* Initialize all of memory for ECC, then
 336                  * enable errors */
 337                 uint *p = 0;
 338                 uint i = 0;
 339                 volatile immap_t *immap = (immap_t *)CFG_IMMR;
 340                 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 341                 dma_init();
 342                 for (*p = 0; p < (uint *)(8 * 1024); p++) {
 343                         if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
 344                         *p = (unsigned int)0xdeadbeef;
 345                         if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
 346                 }
 347
 348                 /* 8K */
 349                 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
 350                 /* 16K */
 351                 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
 352                 /* 32K */
 353                 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
 354                 /* 64K */
 355                 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
 356                 /* 128k */
 357                 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
 358                 /* 256k */
 359                 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
 360                 /* 512k */
 361                 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
 362                 /* 1M */
 363                 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
 364                 /* 2M */
 365                 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
 366                 /* 4M */
 367                 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
 368
 369                 for (i = 1; i < dram_size / 0x800000; i++) {
 370                         dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
 371                 }
 372
 373                 /* Enable errors for ECC */
 374                 ddr->err_disable = 0x00000000;
 375                 asm("sync;isync;msync");
 376         }
 377 #endif
 378
 379         return dram_size;
 380 }
 381
 382
 383 #if defined(CFG_DRAM_TEST)
 384 int testdram (void)
 385 {
 386         uint *pstart = (uint *) CFG_MEMTEST_START;
 387         uint *pend = (uint *) CFG_MEMTEST_END;
 388         uint *p;
 389
 390         printf("SDRAM test phase 1:\n");
 391         for (p = pstart; p < pend; p++)
 392                 *p = 0xaaaaaaaa;
 393
 394         for (p = pstart; p < pend; p++) {
 395                 if (*p != 0xaaaaaaaa) {
 396                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 397                         return 1;
 398                 }
 399         }
 400
 401         printf("SDRAM test phase 2:\n");
 402         for (p = pstart; p < pend; p++)
 403                 *p = 0x55555555;
 404
 405         for (p = pstart; p < pend; p++) {
 406                 if (*p != 0x55555555) {
 407                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 408                         return 1;
 409                 }
 410         }
 411
 412         printf("SDRAM test passed.\n");
 413         return 0;
 414 }
 415 #endif
 416
 417 #if !defined(CONFIG_SPD_EEPROM)
 418 /*************************************************************************
 419  *  fixed sdram init -- doesn't use serial presence detect.
 420  ************************************************************************/
 421 long int fixed_sdram (void)
 422 {
 423
 424 #define CFG_DDR_CONTROL 0xc2000000
 425
 426   #ifndef CFG_RAMBOOT
 427         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 428         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 429
 430         ddr->cs0_bnds           = 0x00000007;
 431         ddr->cs1_bnds           = 0x0010001f;
 432         ddr->cs2_bnds           = 0x00000000;
 433         ddr->cs3_bnds           = 0x00000000;
 434         ddr->cs0_config         = 0x80000102;
 435         ddr->cs1_config         = 0x80000102;
 436         ddr->cs2_config         = 0x00000000;
 437         ddr->cs3_config         = 0x00000000;
 438         ddr->timing_cfg_1       = 0x37334321;
 439         ddr->timing_cfg_2       = 0x00000800;
 440         ddr->sdram_cfg          = 0x42000000;
 441         ddr->sdram_mode         = 0x00000022;
 442         ddr->sdram_interval     = 0x05200100;
 443         ddr->err_sbe            = 0x00ff0000;
 444     #if defined (CONFIG_DDR_ECC)
 445         ddr->err_disable = 0x0000000D;
 446     #endif
 447         asm("sync;isync;msync");
 448         udelay(500);
 449     #if defined (CONFIG_DDR_ECC)
 450         /* Enable ECC checking */
 451         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
 452     #else
 453         ddr->sdram_cfg = CFG_DDR_CONTROL;
 454     #endif
 455         asm("sync; isync; msync");
 456         udelay(500);
 457   #endif
 458         return CFG_SDRAM_SIZE * 1024 * 1024;
 459 }
 460 #endif  /* !defined(CONFIG_SPD_EEPROM) */