board/sbc8560/sbc8560.c

   1 /*
   2  * (C) Copyright 2003,Motorola Inc.
   3  * Xianghua Xiao, (X.Xiao@motorola.com)
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   8  * Added support for Wind River SBC8560 board
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29
  30 #include <common.h>
  31 #include <asm/processor.h>
  32 #include <asm/immap_85xx.h>
  33 #include <ioports.h>
  34 #include <spd_sdram.h>
  35 #include <miiphy.h>
  36 #include <libfdt.h>
  37 #include <fdt_support.h>
  38
  39 long int fixed_sdram (void);
  40
  41 /*
  42  * I/O Port configuration table
  43  *
  44  * if conf is 1, then that port pin will be configured at boot time
  45  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  46  */
  47
  48 const iop_conf_t iop_conf_tab[4][32] = {
  49
  50     /* Port A configuration */
  51     {   /*            conf ppar psor pdir podr pdat */
  52         /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  53         /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  54         /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  55         /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  56         /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  57         /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  58         /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  59         /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  60         /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  61         /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  62         /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  63         /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  64         /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  65         /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  66         /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  67         /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  68         /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  69         /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  70         /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  71         /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  72         /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  73         /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  74         /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  75         /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  76         /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  77         /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  78         /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  79         /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  80         /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  81         /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  82         /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  83         /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  84     },
  85
  86     /* Port B configuration */
  87     {   /*            conf ppar psor pdir podr pdat */
  88         /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  89         /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  90         /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
  91         /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
  92         /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
  93         /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
  94         /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
  95         /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
  96         /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
  97         /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
  98         /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
  99         /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 100         /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 101         /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 102         /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 103         /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 104         /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 105         /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 106         /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 107         /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 108         /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 109         /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 110         /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 111         /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 112         /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 113         /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 114         /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 115         /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 116         /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 117         /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 118         /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 119         /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 120     },
 121
 122     /* Port C */
 123     {   /*            conf ppar psor pdir podr pdat */
 124         /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 125         /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 126         /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 127         /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 128         /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 129         /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 130         /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 131         /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 132         /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 133         /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 134         /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 135         /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 136         /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 137         /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 138         /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 139         /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 140         /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 141         /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 142         /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 143         /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 144         /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 145         /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 146         /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 147         /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 148         /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 149         /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 150         /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 151         /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 152         /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 153         /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 154         /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 155         /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 156     },
 157
 158     /* Port D */
 159     {   /*            conf ppar psor pdir podr pdat */
 160         /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 161         /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 162         /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
 163         /* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
 164         /* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
 165         /* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
 166         /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 167         /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 168         /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 169         /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 170         /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 171         /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 172         /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 173         /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 174         /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 175         /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 176         /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 177         /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 178         /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 179         /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 180         /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 181         /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 182         /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 183         /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 184         /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 185         /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 186         /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 187         /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 188         /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 189         /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 190         /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 191         /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 192     }
 193 };
 194
 195 int board_early_init_f (void)
 196 {
 197 #if defined(CONFIG_PCI)
 198     volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 199
 200     pci->peer &= 0xfffffffdf; /* disable master abort */
 201 #endif
 202         return 0;
 203 }
 204
 205 void reset_phy (void)
 206 {
 207 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
 208         volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
 209 #endif
 210         /* reset Giga bit Ethernet port if needed here */
 211
 212         /* reset the CPM FEC port */
 213 #if (CONFIG_ETHER_INDEX == 2)
 214         bcsr[0] &= ~0x20;
 215         udelay(2);
 216         bcsr[0] |= 0x20;
 217         udelay(1000);
 218 #elif (CONFIG_ETHER_INDEX == 3)
 219         bcsr[0] &= ~0x10;
 220         udelay(2);
 221         bcsr[0] |= 0x10;
 222         udelay(1000);
 223 #endif
 224 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
 225         /* reset PHY */
 226         miiphy_reset("FCC1 ETHERNET", 0x0);
 227
 228         /* change PHY address to 0x02 */
 229         bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
 230
 231         bb_miiphy_write(NULL, 0x02, PHY_BMCR,
 232                         PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 233 #endif /* CONFIG_MII */
 234 }
 235
 236 int checkboard (void)
 237 {
 238         sys_info_t sysinfo;
 239
 240         get_sys_info (&sysinfo);
 241
 242 #ifdef CONFIG_SBC8560
 243         printf ("Board: Wind River SBC8560 Board\n");
 244 #else
 245         printf ("Board: Wind River SBC8540 Board\n");
 246 #endif
 247         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 248         printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
 249         printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
 250         if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
 251                 || (CFG_LBC_LCRR & 0x0f) == 8) {
 252                 printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
 253         } else {
 254                 printf("\tLBC: unknown\n");
 255         }
 256         printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
 257         printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
 258         return (0);
 259 }
 260
 261
 262 phys_size_t initdram (int board_type)
 263 {
 264         long dram_size = 0;
 265
 266 #if 0
 267 #if !defined(CONFIG_RAM_AS_FLASH)
 268         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
 269         sys_info_t sysinfo;
 270         uint temp_lbcdll = 0;
 271 #endif
 272 #endif /* 0 */
 273 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
 274         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 275 #endif
 276 #if defined(CONFIG_DDR_DLL)
 277         uint temp_ddrdll = 0;
 278
 279         /* Work around to stabilize DDR DLL */
 280         temp_ddrdll = gur->ddrdllcr;
 281         gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
 282         asm("sync;isync;msync");
 283 #endif
 284
 285 #if defined(CONFIG_SPD_EEPROM)
 286         dram_size = spd_sdram ();
 287 #else
 288         dram_size = fixed_sdram ();
 289 #endif
 290
 291 #if 0
 292 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
 293         get_sys_info(&sysinfo);
 294         /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
 295         if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
 296                 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
 297         } else {
 298 #if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
 299                 lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
 300 #endif
 301                 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
 302                 udelay(200);
 303                 temp_lbcdll = gur->lbcdllcr;
 304                 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 305                 asm("sync;isync;msync");
 306         }
 307         lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
 308         lbc->br2 = CFG_BR2_PRELIM;
 309         lbc->lbcr = CFG_LBC_LBCR;
 310         lbc->lsdmr = CFG_LBC_LSDMR_1;
 311         asm("sync");
 312         (unsigned int) * (ulong *)0 = 0x000000ff;
 313         lbc->lsdmr = CFG_LBC_LSDMR_2;
 314         asm("sync");
 315         (unsigned int) * (ulong *)0 = 0x000000ff;
 316         lbc->lsdmr = CFG_LBC_LSDMR_3;
 317         asm("sync");
 318         (unsigned int) * (ulong *)0 = 0x000000ff;
 319         lbc->lsdmr = CFG_LBC_LSDMR_4;
 320         asm("sync");
 321         (unsigned int) * (ulong *)0 = 0x000000ff;
 322         lbc->lsdmr = CFG_LBC_LSDMR_5;
 323         asm("sync");
 324         lbc->lsrt = CFG_LBC_LSRT;
 325         asm("sync");
 326         lbc->mrtpr = CFG_LBC_MRTPR;
 327         asm("sync");
 328 #endif
 329 #endif
 330
 331 #if defined(CONFIG_DDR_ECC)
 332         {
 333                 /* Initialize all of memory for ECC, then
 334                  * enable errors */
 335                 uint *p = 0;
 336                 uint i = 0;
 337                 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 338                 dma_init();
 339                 for (*p = 0; p < (uint *)(8 * 1024); p++) {
 340                         if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
 341                         *p = (unsigned int)0xdeadbeef;
 342                         if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
 343                 }
 344
 345                 /* 8K */
 346                 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
 347                 /* 16K */
 348                 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
 349                 /* 32K */
 350                 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
 351                 /* 64K */
 352                 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
 353                 /* 128k */
 354                 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
 355                 /* 256k */
 356                 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
 357                 /* 512k */
 358                 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
 359                 /* 1M */
 360                 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
 361                 /* 2M */
 362                 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
 363                 /* 4M */
 364                 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
 365
 366                 for (i = 1; i < dram_size / 0x800000; i++) {
 367                         dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
 368                 }
 369
 370                 /* Enable errors for ECC */
 371                 ddr->err_disable = 0x00000000;
 372                 asm("sync;isync;msync");
 373         }
 374 #endif
 375
 376         return dram_size;
 377 }
 378
 379
 380 #if defined(CFG_DRAM_TEST)
 381 int testdram (void)
 382 {
 383         uint *pstart = (uint *) CFG_MEMTEST_START;
 384         uint *pend = (uint *) CFG_MEMTEST_END;
 385         uint *p;
 386
 387         printf("SDRAM test phase 1:\n");
 388         for (p = pstart; p < pend; p++)
 389                 *p = 0xaaaaaaaa;
 390
 391         for (p = pstart; p < pend; p++) {
 392                 if (*p != 0xaaaaaaaa) {
 393                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 394                         return 1;
 395                 }
 396         }
 397
 398         printf("SDRAM test phase 2:\n");
 399         for (p = pstart; p < pend; p++)
 400                 *p = 0x55555555;
 401
 402         for (p = pstart; p < pend; p++) {
 403                 if (*p != 0x55555555) {
 404                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 405                         return 1;
 406                 }
 407         }
 408
 409         printf("SDRAM test passed.\n");
 410         return 0;
 411 }
 412 #endif
 413
 414 #if !defined(CONFIG_SPD_EEPROM)
 415 /*************************************************************************
 416  *  fixed sdram init -- doesn't use serial presence detect.
 417  ************************************************************************/
 418 long int fixed_sdram (void)
 419 {
 420
 421 #define CFG_DDR_CONTROL 0xc2000000
 422
 423   #ifndef CFG_RAMBOOT
 424         volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 425
 426 #if (CFG_SDRAM_SIZE == 512)
 427         ddr->cs0_bnds           = 0x0000000f;
 428 #else
 429         ddr->cs0_bnds           = 0x00000007;
 430 #endif
 431         ddr->cs1_bnds           = 0x0010001f;
 432         ddr->cs2_bnds           = 0x00000000;
 433         ddr->cs3_bnds           = 0x00000000;
 434         ddr->cs0_config         = 0x80000102;
 435         ddr->cs1_config         = 0x80000102;
 436         ddr->cs2_config         = 0x00000000;
 437         ddr->cs3_config         = 0x00000000;
 438         ddr->timing_cfg_1       = 0x37334321;
 439         ddr->timing_cfg_2       = 0x00000800;
 440         ddr->sdram_cfg          = 0x42000000;
 441         ddr->sdram_mode         = 0x00000022;
 442         ddr->sdram_interval     = 0x05200100;
 443         ddr->err_sbe            = 0x00ff0000;
 444     #if defined (CONFIG_DDR_ECC)
 445         ddr->err_disable = 0x0000000D;
 446     #endif
 447         asm("sync;isync;msync");
 448         udelay(500);
 449     #if defined (CONFIG_DDR_ECC)
 450         /* Enable ECC checking */
 451         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
 452     #else
 453         ddr->sdram_cfg = CFG_DDR_CONTROL;
 454     #endif
 455         asm("sync; isync; msync");
 456         udelay(500);
 457   #endif
 458         return CFG_SDRAM_SIZE * 1024 * 1024;
 459 }
 460 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 461
 462
 463 #if defined(CONFIG_OF_BOARD_SETUP)
 464 void
 465 ft_board_setup(void *blob, bd_t *bd)
 466 {
 467         int node, tmp[2];
 468 #ifdef CONFIG_PCI
 469         const char *path;
 470 #endif
 471
 472         ft_cpu_setup(blob, bd);
 473
 474         node = fdt_path_offset(blob, "/aliases");
 475         tmp[0] = 0;
 476         if (node >= 0) {
 477 #ifdef CONFIG_PCI
 478                 path = fdt_getprop(blob, node, "pci0", NULL);
 479                 if (path) {
 480                         tmp[1] = hose.last_busno - hose.first_busno;
 481                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 482                 }
 483 #endif
 484         }
 485 }
 486 #endif