2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman joe.hamman@embeddedspecialties.com
6 * Copyright 2004 Freescale Semiconductor.
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
12 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
19 #include <asm/immap_86xx.h>
20 #include <asm/fsl_pci.h>
21 #include <fsl_ddr_sdram.h>
22 #include <asm/fsl_serdes.h>
24 #include <fdt_support.h>
26 long int fixed_sdram (void);
28 int board_early_init_f (void)
35 puts ("Board: Wind River SBC8641D\n");
40 phys_size_t
initdram (int board_type
)
44 #if defined(CONFIG_SPD_EEPROM)
45 dram_size
= fsl_ddr_sdram();
47 dram_size
= fixed_sdram ();
54 #if defined(CONFIG_SYS_DRAM_TEST)
57 uint
*pstart
= (uint
*) CONFIG_SYS_MEMTEST_START
;
58 uint
*pend
= (uint
*) CONFIG_SYS_MEMTEST_END
;
61 puts ("SDRAM test phase 1:\n");
62 for (p
= pstart
; p
< pend
; p
++)
65 for (p
= pstart
; p
< pend
; p
++) {
66 if (*p
!= 0xaaaaaaaa) {
67 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
72 puts ("SDRAM test phase 2:\n");
73 for (p
= pstart
; p
< pend
; p
++)
76 for (p
= pstart
; p
< pend
; p
++) {
77 if (*p
!= 0x55555555) {
78 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
83 puts ("SDRAM test passed.\n");
88 #if !defined(CONFIG_SPD_EEPROM)
90 * Fixed sdram init -- doesn't use serial presence detect.
92 long int fixed_sdram (void)
94 #if !defined(CONFIG_SYS_RAMBOOT)
95 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
96 volatile struct ccsr_ddr
*ddr
= &immap
->im_ddr1
;
98 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
99 ddr
->cs1_bnds
= CONFIG_SYS_DDR_CS1_BNDS
;
100 ddr
->cs2_bnds
= CONFIG_SYS_DDR_CS2_BNDS
;
101 ddr
->cs3_bnds
= CONFIG_SYS_DDR_CS3_BNDS
;
102 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
103 ddr
->cs1_config
= CONFIG_SYS_DDR_CS1_CONFIG
;
104 ddr
->cs2_config
= CONFIG_SYS_DDR_CS2_CONFIG
;
105 ddr
->cs3_config
= CONFIG_SYS_DDR_CS3_CONFIG
;
106 ddr
->timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
107 ddr
->timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
108 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
109 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
110 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CFG_1A
;
111 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR_CFG_2
;
112 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE_1
;
113 ddr
->sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
;
114 ddr
->sdram_md_cntl
= CONFIG_SYS_DDR_MODE_CTL
;
115 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
116 ddr
->sdram_data_init
= CONFIG_SYS_DDR_DATA_INIT
;
117 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
;
123 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CFG_1B
;
127 ddr
= &immap
->im_ddr2
;
129 ddr
->cs0_bnds
= CONFIG_SYS_DDR2_CS0_BNDS
;
130 ddr
->cs1_bnds
= CONFIG_SYS_DDR2_CS1_BNDS
;
131 ddr
->cs2_bnds
= CONFIG_SYS_DDR2_CS2_BNDS
;
132 ddr
->cs3_bnds
= CONFIG_SYS_DDR2_CS3_BNDS
;
133 ddr
->cs0_config
= CONFIG_SYS_DDR2_CS0_CONFIG
;
134 ddr
->cs1_config
= CONFIG_SYS_DDR2_CS1_CONFIG
;
135 ddr
->cs2_config
= CONFIG_SYS_DDR2_CS2_CONFIG
;
136 ddr
->cs3_config
= CONFIG_SYS_DDR2_CS3_CONFIG
;
137 ddr
->timing_cfg_3
= CONFIG_SYS_DDR2_EXT_REFRESH
;
138 ddr
->timing_cfg_0
= CONFIG_SYS_DDR2_TIMING_0
;
139 ddr
->timing_cfg_1
= CONFIG_SYS_DDR2_TIMING_1
;
140 ddr
->timing_cfg_2
= CONFIG_SYS_DDR2_TIMING_2
;
141 ddr
->sdram_cfg
= CONFIG_SYS_DDR2_CFG_1A
;
142 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR2_CFG_2
;
143 ddr
->sdram_mode
= CONFIG_SYS_DDR2_MODE_1
;
144 ddr
->sdram_mode_2
= CONFIG_SYS_DDR2_MODE_2
;
145 ddr
->sdram_md_cntl
= CONFIG_SYS_DDR2_MODE_CTL
;
146 ddr
->sdram_interval
= CONFIG_SYS_DDR2_INTERVAL
;
147 ddr
->sdram_data_init
= CONFIG_SYS_DDR2_DATA_INIT
;
148 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR2_CLK_CTRL
;
154 ddr
->sdram_cfg
= CONFIG_SYS_DDR2_CFG_1B
;
159 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
161 #endif /* !defined(CONFIG_SPD_EEPROM) */
163 #if defined(CONFIG_PCI)
165 * Initialize PCI Devices, report devices found.
168 void pci_init_board(void)
170 fsl_pcie_init_board(0);
172 #endif /* CONFIG_PCI */
175 #if defined(CONFIG_OF_BOARD_SETUP)
176 int ft_board_setup(void *blob
, bd_t
*bd
)
178 ft_cpu_setup(blob
, bd
);
186 void sbc8641d_reset_board (void)
188 puts ("Resetting board....\n");
193 * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
196 unsigned long get_board_sys_clk (ulong dummy
)
234 void board_reset(void)
236 #ifdef CONFIG_SYS_RESET_ADDRESS
237 ulong addr
= CONFIG_SYS_RESET_ADDRESS
;
239 /* flush and disable I/D cache */
240 __asm__
__volatile__ ("mfspr 3, 1008" ::: "r3");
241 __asm__
__volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
242 __asm__
__volatile__ ("ori 4, 3, 0xc00" ::: "r4");
243 __asm__
__volatile__ ("andc 5, 3, 5" ::: "r5");
244 __asm__
__volatile__ ("sync");
245 __asm__
__volatile__ ("mtspr 1008, 4");
246 __asm__
__volatile__ ("isync");
247 __asm__
__volatile__ ("sync");
248 __asm__
__volatile__ ("mtspr 1008, 5");
249 __asm__
__volatile__ ("isync");
250 __asm__
__volatile__ ("sync");
253 * SRR0 has system reset vector, SRR1 has default MSR value
254 * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
256 __asm__
__volatile__ ("mtspr 26, %0" :: "r" (addr
));
257 __asm__
__volatile__ ("li 4, (1 << 6)" ::: "r4");
258 __asm__
__volatile__ ("mtspr 27, 4");
259 __asm__
__volatile__ ("rfi");