board/sbc8641d/sbc8641d.c

   1 /*
   2  * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Joe Hamman joe.hamman@embeddedspecialties.com
   5  *
   6  * Copyright 2004 Freescale Semiconductor.
   7  * Jeff Brown
   8  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9  *
  10  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32 #include <command.h>
  33 #include <pci.h>
  34 #include <asm/processor.h>
  35 #include <asm/immap_86xx.h>
  36 #include <asm/immap_fsl_pci.h>
  37 #include <spd.h>
  38 #include <libfdt.h>
  39 #include <fdt_support.h>
  40
  41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  42 extern void ddr_enable_ecc (unsigned int dram_size);
  43 #endif
  44
  45 #if defined(CONFIG_SPD_EEPROM)
  46 #include "spd_sdram.h"
  47 #endif
  48
  49 void sdram_init (void);
  50 long int fixed_sdram (void);
  51
  52 int board_early_init_f (void)
  53 {
  54         return 0;
  55 }
  56
  57 int checkboard (void)
  58 {
  59         puts ("Board: Wind River SBC8641D\n");
  60
  61         return 0;
  62 }
  63
  64 long int initdram (int board_type)
  65 {
  66         long dram_size = 0;
  67
  68 #if defined(CONFIG_SPD_EEPROM)
  69         dram_size = spd_sdram ();
  70 #else
  71         dram_size = fixed_sdram ();
  72 #endif
  73
  74 #if defined(CFG_RAMBOOT)
  75         puts ("    DDR: ");
  76         return dram_size;
  77 #endif
  78
  79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  80         /*
  81          * Initialize and enable DDR ECC.
  82          */
  83         ddr_enable_ecc (dram_size);
  84 #endif
  85
  86         puts ("    DDR: ");
  87         return dram_size;
  88 }
  89
  90 #if defined(CFG_DRAM_TEST)
  91 int testdram (void)
  92 {
  93         uint *pstart = (uint *) CFG_MEMTEST_START;
  94         uint *pend = (uint *) CFG_MEMTEST_END;
  95         uint *p;
  96
  97         puts ("SDRAM test phase 1:\n");
  98         for (p = pstart; p < pend; p++)
  99                 *p = 0xaaaaaaaa;
 100
 101         for (p = pstart; p < pend; p++) {
 102                 if (*p != 0xaaaaaaaa) {
 103                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 104                         return 1;
 105                 }
 106         }
 107
 108         puts ("SDRAM test phase 2:\n");
 109         for (p = pstart; p < pend; p++)
 110                 *p = 0x55555555;
 111
 112         for (p = pstart; p < pend; p++) {
 113                 if (*p != 0x55555555) {
 114                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 115                         return 1;
 116                 }
 117         }
 118
 119         puts ("SDRAM test passed.\n");
 120         return 0;
 121 }
 122 #endif
 123
 124 #if !defined(CONFIG_SPD_EEPROM)
 125 /*
 126  * Fixed sdram init -- doesn't use serial presence detect.
 127  */
 128 long int fixed_sdram (void)
 129 {
 130 #if !defined(CFG_RAMBOOT)
 131         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 132         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 133
 134         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 135         ddr->cs1_bnds = CFG_DDR_CS1_BNDS;
 136         ddr->cs2_bnds = CFG_DDR_CS2_BNDS;
 137         ddr->cs3_bnds = CFG_DDR_CS3_BNDS;
 138         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 139         ddr->cs1_config = CFG_DDR_CS1_CONFIG;
 140         ddr->cs2_config = CFG_DDR_CS2_CONFIG;
 141         ddr->cs3_config = CFG_DDR_CS3_CONFIG;
 142         ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
 143         ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
 144         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 145         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 146         ddr->sdram_cfg_1 = CFG_DDR_CFG_1A;
 147         ddr->sdram_cfg_2 = CFG_DDR_CFG_2;
 148         ddr->sdram_mode_1 = CFG_DDR_MODE_1;
 149         ddr->sdram_mode_2 = CFG_DDR_MODE_2;
 150         ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL;
 151         ddr->sdram_interval = CFG_DDR_INTERVAL;
 152         ddr->sdram_data_init = CFG_DDR_DATA_INIT;
 153         ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
 154
 155         asm ("sync;isync");
 156
 157         udelay (500);
 158
 159         ddr->sdram_cfg_1 = CFG_DDR_CFG_1B;
 160         asm ("sync; isync");
 161
 162         udelay (500);
 163         ddr = &immap->im_ddr2;
 164
 165         ddr->cs0_bnds = CFG_DDR2_CS0_BNDS;
 166         ddr->cs1_bnds = CFG_DDR2_CS1_BNDS;
 167         ddr->cs2_bnds = CFG_DDR2_CS2_BNDS;
 168         ddr->cs3_bnds = CFG_DDR2_CS3_BNDS;
 169         ddr->cs0_config = CFG_DDR2_CS0_CONFIG;
 170         ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
 171         ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
 172         ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
 173         ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
 174         ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
 175         ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
 176         ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
 177         ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A;
 178         ddr->sdram_cfg_2 = CFG_DDR2_CFG_2;
 179         ddr->sdram_mode_1 = CFG_DDR2_MODE_1;
 180         ddr->sdram_mode_2 = CFG_DDR2_MODE_2;
 181         ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL;
 182         ddr->sdram_interval = CFG_DDR2_INTERVAL;
 183         ddr->sdram_data_init = CFG_DDR2_DATA_INIT;
 184         ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL;
 185
 186         asm ("sync;isync");
 187
 188         udelay (500);
 189
 190         ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B;
 191         asm ("sync; isync");
 192
 193         udelay (500);
 194 #endif
 195         return CFG_SDRAM_SIZE * 1024 * 1024;
 196 }
 197 #endif                          /* !defined(CONFIG_SPD_EEPROM) */
 198
 199 #if defined(CONFIG_PCI)
 200 /*
 201  * Initialize PCI Devices, report devices found.
 202  */
 203
 204 #ifndef CONFIG_PCI_PNP
 205 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 206         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 207          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 208          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 209                                      PCI_ENET0_MEMADDR,
 210                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 211         {}
 212 };
 213 #endif
 214
 215 static struct pci_controller pci1_hose = {
 216 #ifndef CONFIG_PCI_PNP
 217         config_table:pci_mpc86xxcts_config_table
 218 #endif
 219 };
 220 #endif /* CONFIG_PCI */
 221
 222 #ifdef CONFIG_PCI2
 223 static struct pci_controller pci2_hose;
 224 #endif  /* CONFIG_PCI2 */
 225
 226 int first_free_busno = 0;
 227
 228 void pci_init_board(void)
 229 {
 230         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 231         volatile ccsr_gur_t *gur = &immap->im_gur;
 232         uint devdisr = gur->devdisr;
 233         uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 234                 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 235
 236 #ifdef CONFIG_PCI1
 237 {
 238         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 239         extern void fsl_pci_init(struct pci_controller *hose);
 240         struct pci_controller *hose = &pci1_hose;
 241 #ifdef DEBUG
 242         uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
 243                 >> MPC8641_PORBMSR_HA_SHIFT;
 244         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 245 #endif
 246         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
 247              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
 248             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
 249                 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
 250                 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
 251                 if (pci->pme_msg_det) {
 252                         pci->pme_msg_det = 0xffffffff;
 253                         debug(" with errors.  Clearing.  Now 0x%08x",
 254                               pci->pme_msg_det);
 255                 }
 256                 debug("\n");
 257
 258                 /* inbound */
 259                 pci_set_region(hose->regions + 0,
 260                                CFG_PCI_MEMORY_BUS,
 261                                CFG_PCI_MEMORY_PHYS,
 262                                CFG_PCI_MEMORY_SIZE,
 263                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 264
 265                 /* outbound memory */
 266                 pci_set_region(hose->regions + 1,
 267                                CFG_PCI1_MEM_BASE,
 268                                CFG_PCI1_MEM_PHYS,
 269                                CFG_PCI1_MEM_SIZE,
 270                                PCI_REGION_MEM);
 271
 272                 /* outbound io */
 273                 pci_set_region(hose->regions + 2,
 274                                CFG_PCI1_IO_BASE,
 275                                CFG_PCI1_IO_PHYS,
 276                                CFG_PCI1_IO_SIZE,
 277                                PCI_REGION_IO);
 278
 279                 hose->region_count = 3;
 280
 281                 hose->first_busno=first_free_busno;
 282                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 283
 284                 fsl_pci_init(hose);
 285
 286                 first_free_busno=hose->last_busno+1;
 287                 printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
 288                         hose->first_busno,hose->last_busno);
 289
 290         } else {
 291                 puts("PCI-EXPRESS 1: Disabled\n");
 292         }
 293 }
 294 #else
 295         puts("PCI-EXPRESS1: Disabled\n");
 296 #endif /* CONFIG_PCI1 */
 297
 298 #ifdef CONFIG_PCI2
 299 {
 300         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
 301         extern void fsl_pci_init(struct pci_controller *hose);
 302         struct pci_controller *hose = &pci2_hose;
 303
 304
 305         /* inbound */
 306         pci_set_region(hose->regions + 0,
 307                        CFG_PCI_MEMORY_BUS,
 308                        CFG_PCI_MEMORY_PHYS,
 309                        CFG_PCI_MEMORY_SIZE,
 310                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 311
 312         /* outbound memory */
 313         pci_set_region(hose->regions + 1,
 314                        CFG_PCI2_MEM_BASE,
 315                        CFG_PCI2_MEM_PHYS,
 316                        CFG_PCI2_MEM_SIZE,
 317                        PCI_REGION_MEM);
 318
 319         /* outbound io */
 320         pci_set_region(hose->regions + 2,
 321                        CFG_PCI2_IO_BASE,
 322                        CFG_PCI2_IO_PHYS,
 323                        CFG_PCI2_IO_SIZE,
 324                        PCI_REGION_IO);
 325
 326         hose->region_count = 3;
 327
 328         hose->first_busno=first_free_busno;
 329         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 330
 331         fsl_pci_init(hose);
 332
 333         first_free_busno=hose->last_busno+1;
 334         printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
 335                 hose->first_busno,hose->last_busno);
 336 }
 337 #else
 338         puts("PCI-EXPRESS 2: Disabled\n");
 339 #endif /* CONFIG_PCI2 */
 340
 341 }
 342
 343
 344 #if defined(CONFIG_OF_BOARD_SETUP)
 345
 346 void
 347 ft_board_setup (void *blob, bd_t *bd)
 348 {
 349         int node, tmp[2];
 350         const char *path;
 351
 352         ft_cpu_setup(blob, bd);
 353
 354         node = fdt_path_offset(blob, "/aliases");
 355         tmp[0] = 0;
 356         if (node >= 0) {
 357 #ifdef CONFIG_PCI1
 358                 path = fdt_getprop(blob, node, "pci0", NULL);
 359                 if (path) {
 360                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 361                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 362                 }
 363 #endif
 364 #ifdef CONFIG_PCI2
 365                 path = fdt_getprop(blob, node, "pci1", NULL);
 366                 if (path) {
 367                         tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
 368                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 369                 }
 370 #endif
 371         }
 372 }
 373 #endif
 374
 375 void sbc8641d_reset_board (void)
 376 {
 377         puts ("Resetting board....\n");
 378 }
 379
 380 /*
 381  * get_board_sys_clk
 382  *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
 383  */
 384
 385 unsigned long get_board_sys_clk (ulong dummy)
 386 {
 387         int i;
 388         ulong val = 0;
 389
 390         i = 5;
 391         i &= 0x07;
 392
 393         switch (i) {
 394         case 0:
 395                 val = 33000000;
 396                 break;
 397         case 1:
 398                 val = 40000000;
 399                 break;
 400         case 2:
 401                 val = 50000000;
 402                 break;
 403         case 3:
 404                 val = 66000000;
 405                 break;
 406         case 4:
 407                 val = 83000000;
 408                 break;
 409         case 5:
 410                 val = 100000000;
 411                 break;
 412         case 6:
 413                 val = 134000000;
 414                 break;
 415         case 7:
 416                 val = 166000000;
 417                 break;
 418         }
 419
 420         return val;
 421 }