board/sbc8641d/sbc8641d.c

   1 /*
   2  * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Joe Hamman joe.hamman@embeddedspecialties.com
   5  *
   6  * Copyright 2004 Freescale Semiconductor.
   7  * Jeff Brown
   8  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9  *
  10  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32 #include <command.h>
  33 #include <pci.h>
  34 #include <asm/processor.h>
  35 #include <asm/immap_86xx.h>
  36 #include <spd.h>
  37
  38 #if defined(CONFIG_OF_FLAT_TREE)
  39 #include <ft_build.h>
  40 extern void ft_cpu_setup (void *blob, bd_t * bd);
  41 #endif
  42
  43 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  44 extern void ddr_enable_ecc (unsigned int dram_size);
  45 #endif
  46
  47 #if defined(CONFIG_SPD_EEPROM)
  48 #include "spd_sdram.h"
  49 #endif
  50
  51 void sdram_init (void);
  52 long int fixed_sdram (void);
  53
  54 int board_early_init_f (void)
  55 {
  56         return 0;
  57 }
  58
  59 int checkboard (void)
  60 {
  61         puts ("Board: Wind River SBC8641D\n");
  62
  63 #ifdef CONFIG_PCI
  64
  65         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
  66         volatile ccsr_gur_t *gur = &immap->im_gur;
  67         volatile ccsr_pex_t *pex1 = &immap->im_pex1;
  68
  69         uint devdisr = gur->devdisr;
  70         uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
  71         uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
  72         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
  73
  74         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
  75              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
  76             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
  77                 debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
  78                 debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
  79                 if (pex1->pme_msg_det) {
  80                         pex1->pme_msg_det = 0xffffffff;
  81                         debug (" with errors.  Clearing.  Now 0x%08x",
  82                                pex1->pme_msg_det);
  83                 }
  84                 debug ("\n");
  85         } else {
  86                 puts ("PCI-EXPRESS 1: Disabled in hardware\n");
  87         }
  88
  89 #else
  90         puts ("PCI-EXPRESS1: Disabled in configuration\n");
  91 #endif
  92
  93         return 0;
  94 }
  95
  96 long int initdram (int board_type)
  97 {
  98         long dram_size = 0;
  99
 100 #if defined(CONFIG_SPD_EEPROM)
 101         dram_size = spd_sdram ();
 102 #else
 103         dram_size = fixed_sdram ();
 104 #endif
 105
 106 #if defined(CFG_RAMBOOT)
 107         puts ("    DDR: ");
 108         return dram_size;
 109 #endif
 110
 111 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 112         /*
 113          * Initialize and enable DDR ECC.
 114          */
 115         ddr_enable_ecc (dram_size);
 116 #endif
 117
 118         puts ("    DDR: ");
 119         return dram_size;
 120 }
 121
 122 #if defined(CFG_DRAM_TEST)
 123 int testdram (void)
 124 {
 125         uint *pstart = (uint *) CFG_MEMTEST_START;
 126         uint *pend = (uint *) CFG_MEMTEST_END;
 127         uint *p;
 128
 129         puts ("SDRAM test phase 1:\n");
 130         for (p = pstart; p < pend; p++)
 131                 *p = 0xaaaaaaaa;
 132
 133         for (p = pstart; p < pend; p++) {
 134                 if (*p != 0xaaaaaaaa) {
 135                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 136                         return 1;
 137                 }
 138         }
 139
 140         puts ("SDRAM test phase 2:\n");
 141         for (p = pstart; p < pend; p++)
 142                 *p = 0x55555555;
 143
 144         for (p = pstart; p < pend; p++) {
 145                 if (*p != 0x55555555) {
 146                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 147                         return 1;
 148                 }
 149         }
 150
 151         puts ("SDRAM test passed.\n");
 152         return 0;
 153 }
 154 #endif
 155
 156 #if !defined(CONFIG_SPD_EEPROM)
 157 /*
 158  * Fixed sdram init -- doesn't use serial presence detect.
 159  */
 160 long int fixed_sdram (void)
 161 {
 162 #if !defined(CFG_RAMBOOT)
 163         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 164         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 165
 166         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 167         ddr->cs1_bnds = CFG_DDR_CS1_BNDS;
 168         ddr->cs2_bnds = CFG_DDR_CS2_BNDS;
 169         ddr->cs3_bnds = CFG_DDR_CS3_BNDS;
 170         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 171         ddr->cs1_config = CFG_DDR_CS1_CONFIG;
 172         ddr->cs2_config = CFG_DDR_CS2_CONFIG;
 173         ddr->cs3_config = CFG_DDR_CS3_CONFIG;
 174         ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
 175         ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
 176         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 177         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 178         ddr->sdram_cfg_1 = CFG_DDR_CFG_1A;
 179         ddr->sdram_cfg_2 = CFG_DDR_CFG_2;
 180         ddr->sdram_mode_1 = CFG_DDR_MODE_1;
 181         ddr->sdram_mode_2 = CFG_DDR_MODE_2;
 182         ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL;
 183         ddr->sdram_interval = CFG_DDR_INTERVAL;
 184         ddr->sdram_data_init = CFG_DDR_DATA_INIT;
 185         ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
 186
 187         asm ("sync;isync");
 188
 189         udelay (500);
 190
 191         ddr->sdram_cfg_1 = CFG_DDR_CFG_1B;
 192         asm ("sync; isync");
 193
 194         udelay (500);
 195         ddr = &immap->im_ddr2;
 196
 197         ddr->cs0_bnds = CFG_DDR2_CS0_BNDS;
 198         ddr->cs1_bnds = CFG_DDR2_CS1_BNDS;
 199         ddr->cs2_bnds = CFG_DDR2_CS2_BNDS;
 200         ddr->cs3_bnds = CFG_DDR2_CS3_BNDS;
 201         ddr->cs0_config = CFG_DDR2_CS0_CONFIG;
 202         ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
 203         ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
 204         ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
 205         ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
 206         ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
 207         ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
 208         ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
 209         ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A;
 210         ddr->sdram_cfg_2 = CFG_DDR2_CFG_2;
 211         ddr->sdram_mode_1 = CFG_DDR2_MODE_1;
 212         ddr->sdram_mode_2 = CFG_DDR2_MODE_2;
 213         ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL;
 214         ddr->sdram_interval = CFG_DDR2_INTERVAL;
 215         ddr->sdram_data_init = CFG_DDR2_DATA_INIT;
 216         ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL;
 217
 218         asm ("sync;isync");
 219
 220         udelay (500);
 221
 222         ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B;
 223         asm ("sync; isync");
 224
 225         udelay (500);
 226 #endif
 227         return CFG_SDRAM_SIZE * 1024 * 1024;
 228 }
 229 #endif                          /* !defined(CONFIG_SPD_EEPROM) */
 230
 231 #if defined(CONFIG_PCI)
 232 /*
 233  * Initialize PCI Devices, report devices found.
 234  */
 235
 236 #ifndef CONFIG_PCI_PNP
 237 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 238         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 239          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 240          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 241                                      PCI_ENET0_MEMADDR,
 242                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 243         {}
 244 };
 245 #endif
 246
 247 static struct pci_controller hose = {
 248 #ifndef CONFIG_PCI_PNP
 249       config_table:pci_mpc86xxcts_config_table,
 250 #endif
 251 };
 252
 253 #endif                          /* CONFIG_PCI */
 254
 255 void pci_init_board (void)
 256 {
 257 #ifdef CONFIG_PCI
 258         extern void pci_mpc86xx_init (struct pci_controller *hose);
 259
 260         pci_mpc86xx_init (&hose);
 261 #endif                          /* CONFIG_PCI */
 262 }
 263
 264 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 265 void ft_board_setup (void *blob, bd_t * bd)
 266 {
 267         u32 *p;
 268         int len;
 269
 270         ft_cpu_setup (blob, bd);
 271
 272         p = ft_get_prop (blob, "/memory/reg", &len);
 273         if (p != NULL) {
 274                 *p++ = cpu_to_be32 (bd->bi_memstart);
 275                 *p = cpu_to_be32 (bd->bi_memsize);
 276         }
 277 }
 278 #endif
 279
 280 void sbc8641d_reset_board (void)
 281 {
 282         puts ("Resetting board....\n");
 283 }
 284
 285 /*
 286  * get_board_sys_clk
 287  *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
 288  */
 289
 290 unsigned long get_board_sys_clk (ulong dummy)
 291 {
 292         int i;
 293         ulong val = 0;
 294
 295         i = 5;
 296         i &= 0x07;
 297
 298         switch (i) {
 299         case 0:
 300                 val = 33000000;
 301                 break;
 302         case 1:
 303                 val = 40000000;
 304                 break;
 305         case 2:
 306                 val = 50000000;
 307                 break;
 308         case 3:
 309                 val = 66000000;
 310                 break;
 311         case 4:
 312                 val = 83000000;
 313                 break;
 314         case 5:
 315                 val = 100000000;
 316                 break;
 317         case 6:
 318                 val = 134000000;
 319                 break;
 320         case 7:
 321                 val = 166000000;
 322                 break;
 323         }
 324
 325         return val;
 326 }