board/sbc8641d/sbc8641d.c

   1 /*
   2  * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Joe Hamman joe.hamman@embeddedspecialties.com
   5  *
   6  * Copyright 2004 Freescale Semiconductor.
   7  * Jeff Brown
   8  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9  *
  10  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32 #include <command.h>
  33 #include <pci.h>
  34 #include <asm/processor.h>
  35 #include <asm/immap_86xx.h>
  36 #include <asm/immap_fsl_pci.h>
  37 #include <asm/fsl_ddr_sdram.h>
  38 #include <libfdt.h>
  39 #include <fdt_support.h>
  40
  41 long int fixed_sdram (void);
  42
  43 int board_early_init_f (void)
  44 {
  45         return 0;
  46 }
  47
  48 int checkboard (void)
  49 {
  50         puts ("Board: Wind River SBC8641D\n");
  51
  52         return 0;
  53 }
  54
  55 phys_size_t initdram (int board_type)
  56 {
  57         long dram_size = 0;
  58
  59 #if defined(CONFIG_SPD_EEPROM)
  60         dram_size = fsl_ddr_sdram();
  61 #else
  62         dram_size = fixed_sdram ();
  63 #endif
  64
  65 #if defined(CONFIG_SYS_RAMBOOT)
  66         puts ("    DDR: ");
  67         return dram_size;
  68 #endif
  69
  70         puts ("    DDR: ");
  71         return dram_size;
  72 }
  73
  74 #if defined(CONFIG_SYS_DRAM_TEST)
  75 int testdram (void)
  76 {
  77         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  78         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  79         uint *p;
  80
  81         puts ("SDRAM test phase 1:\n");
  82         for (p = pstart; p < pend; p++)
  83                 *p = 0xaaaaaaaa;
  84
  85         for (p = pstart; p < pend; p++) {
  86                 if (*p != 0xaaaaaaaa) {
  87                         printf ("SDRAM test fails at: %08x\n", (uint) p);
  88                         return 1;
  89                 }
  90         }
  91
  92         puts ("SDRAM test phase 2:\n");
  93         for (p = pstart; p < pend; p++)
  94                 *p = 0x55555555;
  95
  96         for (p = pstart; p < pend; p++) {
  97                 if (*p != 0x55555555) {
  98                         printf ("SDRAM test fails at: %08x\n", (uint) p);
  99                         return 1;
 100                 }
 101         }
 102
 103         puts ("SDRAM test passed.\n");
 104         return 0;
 105 }
 106 #endif
 107
 108 #if !defined(CONFIG_SPD_EEPROM)
 109 /*
 110  * Fixed sdram init -- doesn't use serial presence detect.
 111  */
 112 long int fixed_sdram (void)
 113 {
 114 #if !defined(CONFIG_SYS_RAMBOOT)
 115         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 116         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 117
 118         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 119         ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 120         ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
 121         ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
 122         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 123         ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 124         ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
 125         ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
 126         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 127         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 128         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 129         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 130         ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
 131         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
 132         ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
 133         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 134         ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
 135         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 136         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 137         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 138
 139         asm ("sync;isync");
 140
 141         udelay (500);
 142
 143         ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
 144         asm ("sync; isync");
 145
 146         udelay (500);
 147         ddr = &immap->im_ddr2;
 148
 149         ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
 150         ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
 151         ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
 152         ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
 153         ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
 154         ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
 155         ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
 156         ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
 157         ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
 158         ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
 159         ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
 160         ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
 161         ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
 162         ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
 163         ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
 164         ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
 165         ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
 166         ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
 167         ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
 168         ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
 169
 170         asm ("sync;isync");
 171
 172         udelay (500);
 173
 174         ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
 175         asm ("sync; isync");
 176
 177         udelay (500);
 178 #endif
 179         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 180 }
 181 #endif                          /* !defined(CONFIG_SPD_EEPROM) */
 182
 183 #if defined(CONFIG_PCI)
 184 /*
 185  * Initialize PCI Devices, report devices found.
 186  */
 187
 188 #ifndef CONFIG_PCI_PNP
 189 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 190         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 191          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 192          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 193                                      PCI_ENET0_MEMADDR,
 194                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 195         {}
 196 };
 197 #endif
 198
 199 static struct pci_controller pci1_hose = {
 200 #ifndef CONFIG_PCI_PNP
 201         config_table:pci_mpc86xxcts_config_table
 202 #endif
 203 };
 204 #endif /* CONFIG_PCI */
 205
 206 #ifdef CONFIG_PCI2
 207 static struct pci_controller pci2_hose;
 208 #endif  /* CONFIG_PCI2 */
 209
 210 int first_free_busno = 0;
 211
 212 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
 213 extern void fsl_pci_init(struct pci_controller *hose);
 214
 215 void pci_init_board(void)
 216 {
 217         volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 218         volatile ccsr_gur_t *gur = &immap->im_gur;
 219         uint devdisr = gur->devdisr;
 220         uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 221                 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 222
 223 #ifdef CONFIG_PCI1
 224 {
 225         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 226         struct pci_controller *hose = &pci1_hose;
 227         struct pci_region *r = hose->regions;
 228 #ifdef DEBUG
 229         uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
 230                 >> MPC8641_PORBMSR_HA_SHIFT;
 231         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 232 #endif
 233         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
 234              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
 235             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
 236                 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
 237                 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
 238                 if (pci->pme_msg_det) {
 239                         pci->pme_msg_det = 0xffffffff;
 240                         debug(" with errors.  Clearing.  Now 0x%08x",
 241                               pci->pme_msg_det);
 242                 }
 243                 debug("\n");
 244
 245                 /* inbound */
 246                 r += fsl_pci_setup_inbound_windows(r);
 247
 248                 /* outbound memory */
 249                 pci_set_region(r++,
 250                                CONFIG_SYS_PCI1_MEM_BASE,
 251                                CONFIG_SYS_PCI1_MEM_PHYS,
 252                                CONFIG_SYS_PCI1_MEM_SIZE,
 253                                PCI_REGION_MEM);
 254
 255                 /* outbound io */
 256                 pci_set_region(r++,
 257                                CONFIG_SYS_PCI1_IO_BASE,
 258                                CONFIG_SYS_PCI1_IO_PHYS,
 259                                CONFIG_SYS_PCI1_IO_SIZE,
 260                                PCI_REGION_IO);
 261
 262                 hose->region_count = r - hose->regions;
 263
 264                 hose->first_busno=first_free_busno;
 265                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 266
 267                 fsl_pci_init(hose);
 268
 269                 first_free_busno=hose->last_busno+1;
 270                 printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
 271                         hose->first_busno,hose->last_busno);
 272
 273         } else {
 274                 puts("PCI-EXPRESS 1: Disabled\n");
 275         }
 276 }
 277 #else
 278         puts("PCI-EXPRESS1: Disabled\n");
 279 #endif /* CONFIG_PCI1 */
 280
 281 #ifdef CONFIG_PCI2
 282 {
 283         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 284         struct pci_controller *hose = &pci2_hose;
 285         struct pci_region *r = hose->regions;
 286
 287
 288         /* inbound */
 289         r += fsl_pci_setup_inbound_windows(r);
 290
 291         /* outbound memory */
 292         pci_set_region(r++,
 293                        CONFIG_SYS_PCI2_MEM_BASE,
 294                        CONFIG_SYS_PCI2_MEM_PHYS,
 295                        CONFIG_SYS_PCI2_MEM_SIZE,
 296                        PCI_REGION_MEM);
 297
 298         /* outbound io */
 299         pci_set_region(r++,
 300                        CONFIG_SYS_PCI2_IO_BASE,
 301                        CONFIG_SYS_PCI2_IO_PHYS,
 302                        CONFIG_SYS_PCI2_IO_SIZE,
 303                        PCI_REGION_IO);
 304
 305         hose->region_count = r - hose->regions;
 306
 307         hose->first_busno=first_free_busno;
 308         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 309
 310         fsl_pci_init(hose);
 311
 312         first_free_busno=hose->last_busno+1;
 313         printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
 314                 hose->first_busno,hose->last_busno);
 315 }
 316 #else
 317         puts("PCI-EXPRESS 2: Disabled\n");
 318 #endif /* CONFIG_PCI2 */
 319
 320 }
 321
 322
 323 #if defined(CONFIG_OF_BOARD_SETUP)
 324 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 325                         struct pci_controller *hose);
 326
 327 void ft_board_setup (void *blob, bd_t *bd)
 328 {
 329         ft_cpu_setup(blob, bd);
 330
 331 #ifdef CONFIG_PCI1
 332         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 333 #endif
 334 #ifdef CONFIG_PCI2
 335         ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 336 #endif
 337 }
 338 #endif
 339
 340 void sbc8641d_reset_board (void)
 341 {
 342         puts ("Resetting board....\n");
 343 }
 344
 345 /*
 346  * get_board_sys_clk
 347  *      Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
 348  */
 349
 350 unsigned long get_board_sys_clk (ulong dummy)
 351 {
 352         int i;
 353         ulong val = 0;
 354
 355         i = 5;
 356         i &= 0x07;
 357
 358         switch (i) {
 359         case 0:
 360                 val = 33000000;
 361                 break;
 362         case 1:
 363                 val = 40000000;
 364                 break;
 365         case 2:
 366                 val = 50000000;
 367                 break;
 368         case 3:
 369                 val = 66000000;
 370                 break;
 371         case 4:
 372                 val = 83000000;
 373                 break;
 374         case 5:
 375                 val = 100000000;
 376                 break;
 377         case 6:
 378                 val = 134000000;
 379                 break;
 380         case 7:
 381                 val = 166000000;
 382                 break;
 383         }
 384
 385         return val;
 386 }