board/sc3/init.S

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0 IBM-pibs
   3  */
   4 #include <config.h>
   5 #include <asm/ppc4xx.h>
   6
   7 #include <ppc_asm.tmpl>
   8 #include <ppc_defs.h>
   9
  10 #include <asm/cache.h>
  11 #include <asm/mmu.h>
  12
  13 /**
  14  * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
  15  *
  16  * IMPORTANT: For pass1 this code must run from cache since you can not
  17  * reliably change a peripheral banks timing register (pbxap) while running
  18  * code from that bank. For ex., since we are running from ROM on bank 0, we
  19  * can NOT execute the code that modifies bank 0 timings from ROM, so
  20  * we run it from cache.
  21  *
  22  * Bank 0 - Boot-Flash
  23  * Bank 1 - NAND-Flash
  24  * Bank 2 - ISA bus
  25  * Bank 3 - Second Flash
  26  * Bank 4 - USB controller
  27  */
  28         .globl ext_bus_cntlr_init
  29 ext_bus_cntlr_init:
  30 /*
  31  * We need the current boot up configuration to set correct
  32  * timings into internal flash and external flash
  33  */
  34                 mfdcr r24,CPC0_PSR              /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
  35                                                    0 0 -> 8 bit external ROM
  36                                                    0 1 -> 16 bit internal ROM */
  37                 addi r4,0,2
  38                 srw r24,r24,r4                          /* shift right r24 two positions */
  39                 andi. r24,r24,0x06000
  40 /*
  41  * All calculations are based on 33MHz EBC clock.
  42  *
  43  * First, create a "very slow" timing (~250ns) with burst mode enabled
  44  * This is need for the external flash access
  45  */
  46                 lis r25,0x0800
  47                 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
  48                 ori r25,r25,0x0280
  49 /*
  50  * Second, create a fast timing:
  51  * 90ns first cycle - 3 clock access
  52  * and 90ns burst cycle, plus 1 clock after the last access
  53  * This is used for the internal access
  54  */
  55                 lis r26,0x8900
  56                 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
  57                 ori r26,r26,0x0280
  58 /*
  59  * We can't change settings on CS# if we currently use them.
  60  * -> load a few instructions into cache and run this code from cache
  61  */
  62                 mflr r4                                 /* save link register */
  63                 bl ..getAddr
  64 ..getAddr:
  65                 mflr r3                                 /* get address of ..getAddr */
  66                 mtlr r4                                 /* restore link register */
  67                 addi r4,0,14                            /* set ctr to 10; used to prefetch */
  68                 mtctr r4                                /* 10 cache lines to fit this function
  69                                                         in cache (gives us 8x10=80 instructions) */
  70 ..ebcloop:
  71                 icbt r0,r3                              /* prefetch cache line for addr in r3 */
  72                 addi r3,r3,32                           /* move to next cache line */
  73                 bdnz ..ebcloop                          /* continue for 10 cache lines */
  74 /*
  75  * Delay to ensure all accesses to ROM are complete before changing
  76  * bank 0 timings. 200usec should be enough.
  77  * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  78  */
  79                 lis r3,0x0
  80                 ori r3,r3,0xA000                        /* ensure 200usec have passed since reset */
  81                 mtctr r3
  82 ..spinlp:
  83                 bdnz ..spinlp                           /* spin loop */
  84
  85 /*-----------------------------------------------------------------------
  86  * Memory Bank 0 (BOOT-ROM) initialization
  87  * 0xFFEF00000....0xFFFFFFF
  88  * We only have to change the timing. Mapping is ok by boot-strapping
  89  *----------------------------------------------------------------------- */
  90
  91                 li r4,PB1AP                             /* PB0AP=Peripheral Bank 0 Access Parameters */
  92                 mtdcr EBC0_CFGADDR,r4
  93
  94                 mr r4,r26                               /* assume internal fast flash is boot flash */
  95                 cmpwi r24,0x2000                        /* assumption true? ... */
  96                 beq 1f                                  /* ...yes! */
  97                 mr r4,r25                               /* ...no, use the slow variant */
  98                 mr r25,r26                              /* use this for the other flash */
  99 1:
 100                 mtdcr EBC0_CFGDATA,r4                   /* change timing now */
 101
 102                 li r4,PB0CR                             /* PB0CR=Peripheral Bank 0 Control Register */
 103                 mtdcr EBC0_CFGADDR,r4
 104                 mfdcr r4,EBC0_CFGDATA
 105                 lis r3,0x0001
 106                 ori r3,r3,0x8000                        /* allow reads and writes */
 107                 or r4,r4,r3
 108                 mtdcr EBC0_CFGDATA,r4
 109
 110 /*-----------------------------------------------------------------------
 111  * Memory Bank 3 (Second-Flash) initialization
 112  * 0xF0000000...0xF01FFFFF -> 2MB
 113  *----------------------------------------------------------------------- */
 114
 115                 li r4,PB3AP                             /* Peripheral Bank 1 Access Parameter */
 116                 mtdcr EBC0_CFGADDR,r4
 117                 mtdcr EBC0_CFGDATA,r2                   /* change timing */
 118
 119                 li r4,PB3CR                             /* Peripheral Bank 1 Configuration Registers */
 120                 mtdcr EBC0_CFGADDR,r4
 121
 122                 lis r4,0xF003
 123                 ori r4,r4,0x8000
 124 /*
 125  * Consider boot configuration
 126  */
 127                 xori r24,r24,0x2000                     /* invert current bus width */
 128                 or r4,r4,r24
 129                 mtdcr EBC0_CFGDATA,r4
 130
 131 /*-----------------------------------------------------------------------
 132  * Memory Bank 1 (NAND-Flash) initialization
 133  * 0x77D00000...0x77DFFFFF -> 1MB
 134  * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
 135  * - the setup time is 0ns
 136  * - the hold time is 15ns
 137  * ->
 138  *   - TWT = 0
 139  *   - CSN = 0
 140  *   - OEN = 0
 141  *   - WBN = 0
 142  *   - WBF = 0
 143  *   - TH  = 1
 144  * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
 145  *----------------------------------------------------------------------- */
 146
 147                 li r4,PB1AP                             /* Peripheral Bank 1 Access Parameter */
 148                 mtdcr EBC0_CFGADDR,r4
 149
 150                 lis r4,0x0000
 151                 ori r4,r4,0x0200
 152                 mtdcr EBC0_CFGDATA,r4
 153
 154                 li r4,PB1CR                             /* Peripheral Bank 1 Configuration Registers */
 155                 mtdcr EBC0_CFGADDR,r4
 156
 157                 lis r4,0x77D1
 158                 ori r4,r4,0x8000
 159                 mtdcr EBC0_CFGDATA,r4
 160
 161
 162 /* USB init (without acceleration) */
 163 #ifndef CONFIG_ISP1161_PRESENT
 164                 li r4,PB4AP                             /* PB4AP=Peripheral Bank 4 Access Parameters */
 165                 mtdcr EBC0_CFGADDR,r4
 166                 lis r4,0x0180
 167                 ori r4,r4,0x5940
 168                 mtdcr EBC0_CFGDATA,r4
 169 #endif
 170
 171 /*-----------------------------------------------------------------------
 172  * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
 173  * 0x78000000...0x7BFFFFFF -> 64 MB
 174  * Wir arbeiten bei 33 MHz -> 30ns
 175  *-----------------------------------------------------------------------
 176
 177  A7 (ppc notation) or A24 (standard notation) decides about
 178  the type of access:
 179  A7/A24=0 -> memory cycle
 180  A7/ /A24=1 -> I/O cycle
 181 */
 182                 li r4,PB2AP                             /* PB2AP=Peripheral Bank 2 Access Parameters */
 183                 mtdcr EBC0_CFGADDR,r4
 184 /*
 185  We emulate an ISA access
 186
 187  1. Address active
 188  2. wait 0 EBC clocks -> CSN=0
 189  3. set CS#
 190  4. wait 0 EBC clock -> OEN/WBN=0
 191  5. set OE#/WE#
 192  6. wait 4 clocks (ca. 90ns) and for Ready signal
 193  7. hold for 4 clocks -> TH=4
 194 */
 195
 196 #if 1
 197 /* faster access to isa-bus */
 198                 lis r4,0x0180
 199                 ori r4,r4,0x5940
 200 #else
 201                 lis r4,0x0100
 202                 ori r4,r4,0x0340
 203 #endif
 204                 mtdcr EBC0_CFGDATA,r4
 205
 206 #ifdef IDE_USES_ISA_EMULATION
 207                 li r25,PB5AP                            /* PB5AP=Peripheral Bank 5 Access Parameters */
 208                 mtdcr EBC0_CFGADDR,r25
 209                 mtdcr EBC0_CFGDATA,r4
 210 #endif
 211
 212                 li r25,PB6AP                            /* PB6AP=Peripheral Bank 6 Access Parameters */
 213                 mtdcr EBC0_CFGADDR,r25
 214                 mtdcr EBC0_CFGDATA,r4
 215                 li r25,PB7AP                            /* PB7AP=Peripheral Bank 7 Access Parameters */
 216                 mtdcr EBC0_CFGADDR,r25
 217                 mtdcr EBC0_CFGDATA,r4
 218
 219                 li r25,PB2CR                            /* PB2CR=Peripheral Bank 2 Configuration Register */
 220                 mtdcr EBC0_CFGADDR,r25
 221
 222                 lis r4,0x780B
 223                 ori r4,r4,0xA000
 224                 mtdcr EBC0_CFGDATA,r4
 225 /*
 226  * the other areas are only 1MiB in size
 227  */
 228                 lis r4,0x7401
 229                 ori r4,r4,0xA000
 230
 231                 li r25,PB6CR                            /* PB6CR=Peripheral Bank 6 Configuration Register */
 232                 mtdcr EBC0_CFGADDR,r25
 233                 lis r4,0x7401
 234                 ori r4,r4,0xA000
 235                 mtdcr EBC0_CFGDATA,r4
 236
 237                 li r25,PB7CR                            /* PB7CR=Peripheral Bank 7 Configuration Register */
 238                 mtdcr EBC0_CFGADDR,r25
 239                 lis r4,0x7411
 240                 ori r4,r4,0xA000
 241                 mtdcr EBC0_CFGDATA,r4
 242
 243 #ifndef CONFIG_ISP1161_PRESENT
 244                 li r25,PB4CR                            /* PB4CR=Peripheral Bank 4 Configuration Register */
 245                 mtdcr EBC0_CFGADDR,r25
 246                 lis r4,0x7421
 247                 ori r4,r4,0xA000
 248                 mtdcr EBC0_CFGDATA,r4
 249 #endif
 250 #ifdef IDE_USES_ISA_EMULATION
 251                 li r25,PB5CR                            /* PB5CR=Peripheral Bank 5 Configuration Register */
 252                 mtdcr EBC0_CFGADDR,r25
 253                 lis r4,0x0000
 254                 ori r4,r4,0x0000
 255                 mtdcr EBC0_CFGDATA,r4
 256 #endif
 257
 258 /*-----------------------------------------------------------------------
 259  * Memory bank 4: USB controller Philips ISP6111
 260  * 0x77C00000 ... 0x77CFFFFF
 261  *
 262  * The chip is connected to:
 263  * - CPU CS#4
 264  * - CPU IRQ#2
 265  * - CPU DMA 3
 266  *
 267  * Timing:
 268  * - command to first data: 300ns. Software must ensure this timing!
 269  * - Write pulse: 26ns
 270  * - Read pulse: 33ns
 271  * - read cycle time: 150ns
 272  * - write cycle time: 140ns
 273  *
 274  * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
 275  *
 276  *                        |- 300ns --|
 277  *                |---- 420ns ---|---- 420ns ---| cycle
 278  * CS ############:###____#######:###____#######
 279  * OE ############:####___#######:####___#######
 280  * WE ############:####__########:####__########
 281  *
 282  * ----> 2 clocks RD/WR pulses: 60ns
 283  * ----> CSN: 3 clock, 90ns
 284  * ----> OEN: 1 clocks (read cycle)
 285  * ----> WBN: 1 clocks (write cycle)
 286  * ----> WBE: 2 clocks
 287  * ----> TH: 7 clock, 210ns
 288  * ----> TWT: 7 clocks
 289  *----------------------------------------------------------------------- */
 290
 291 #ifdef CONFIG_ISP1161_PRESENT
 292
 293                 li r4,PB4AP                             /* PB4AP=Peripheral Bank 4 Access Parameters */
 294                 mtdcr EBC0_CFGADDR,r4
 295
 296                 lis r4,0x030D
 297                 ori r4,r4,0x5E80
 298                 mtdcr EBC0_CFGDATA,r4
 299
 300                 li r4,PB4CR                             /* PB2CR=Peripheral Bank 4 Configuration Register */
 301                 mtdcr EBC0_CFGADDR,r4
 302
 303                 lis r4,0x77C1
 304                 ori r4,r4,0xA000
 305                 mtdcr EBC0_CFGDATA,r4
 306
 307 #endif
 308
 309 #ifndef IDE_USES_ISA_EMULATION
 310
 311 /*-----------------------------------------------------------------------
 312  * Memory Bank 5 used for IDE access
 313  *
 314  * Timings for IDE Interface
 315  *
 316  * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
 317  *  70          165             30              PIO-Mode 0, [ns]
 318  *   3            6              1              [Cycles] ----> AP=0x040C0200
 319  *  50          125             20         PIO-Mode 1, [ns]
 320  *   2            5              1              [Cycles] ----> AP=0x03080200
 321  *  30          100             15         PIO-Mode 2, [ns]
 322  *   1            4              1              [Cycles] ----> AP=0x02040200
 323  *  30           80             10         PIO-Mode 3, [ns]
 324  *   1            3              1              [Cycles] ----> AP=0x01840200
 325  *  25           70             10         PIO-Mode 4, [ns]
 326  *   1            3              1              [Cycles] ----> AP=0x01840200
 327  *
 328  *----------------------------------------------------------------------- */
 329
 330                 li r4,PB5AP
 331                 mtdcr EBC0_CFGADDR,r4
 332                 lis r4,0x040C
 333                 ori r4,r4,0x0200
 334                 mtdcr EBC0_CFGDATA,r4
 335
 336                 li r4,PB5CR                     /* PB2CR=Peripheral Bank 2 Configuration Register */
 337                 mtdcr EBC0_CFGADDR,r4
 338
 339                 lis r4,0x7A01
 340                 ori r4,r4,0xA000
 341                 mtdcr EBC0_CFGDATA,r4
 342 #endif
 343 /*
 344  * External Peripheral Control Register
 345  */
 346                 li r4,EBC0_CFG
 347                 mtdcr EBC0_CFGADDR,r4
 348
 349                 lis r4,0xB84E
 350                 ori r4,r4,0xF000
 351                 mtdcr EBC0_CFGDATA,r4
 352 /*
 353  * drive POST code
 354  */
 355                 lis r4,0x7900
 356                 ori r4,r4,0x0080
 357                 li r3,0x0001
 358                 stb r3,0(r4)                    /* 01 -> external bus controller is initialized */
 359                 nop                             /* pass2 DCR errata #8 */
 360                 blr