board/sc3/sc3.c

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
   4  *
   5  * (C) Copyright 2003
   6  * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
   7  * Derived from walnut.c
   8  *
   9  * (C) Copyright 2000
  10  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <asm/processor.h>
  17 #include <asm/io.h>
  18 #include "sc3.h"
  19 #include <pci.h>
  20 #include <i2c.h>
  21 #include <malloc.h>
  22 #include <netdev.h>
  23
  24 #undef writel
  25 #undef writeb
  26 #define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
  27 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
  28
  29 /* write only register to configure things in our CPLD */
  30 #define CPLD_CONTROL_1  0x79000102
  31 #define CPLD_VERSION    0x79000103
  32
  33 #define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
  34
  35 static struct pci_controller hose={0,};
  36
  37 /************************************************************
  38  * Standard definition
  39  ************************************************************/
  40
  41 /* CPC0_CR0        Function                                 ISA bus
  42         -  GPIO0
  43         -  GPIO1      -> Output: NAND-Command Latch Enable
  44         -  GPIO2      -> Output: NAND Address Latch Enable
  45         -  GPIO3      -> IRQ input                               ISA-IRQ #5 (through CPLD)
  46         -  GPIO4      -> Output: NAND-Chip Enable
  47         -  GPIO5      -> IRQ input                               ISA-IRQ#7 (through CPLD)
  48         -  GPIO6      -> IRQ input                               ISA-IRQ#9 (through CPLD)
  49         -  GPIO7      -> IRQ input                               ISA-IRQ#10 (through CPLD)
  50         -  GPIO8      -> IRQ input                               ISA-IRQ#11 (through CPLD)
  51         -  GPIO9      -> IRQ input                               ISA-IRQ#12 (through CPLD)
  52         - GPIO10/CS1# -> CS1# NAND                               ISA-CS#0
  53         - GPIO11/CS2# -> CS2# ISA emulation                      ISA-CS#1
  54         - GPIO12/CS3# -> CS3# 2nd Flash-Bank                     ISA-CS#2 or ISA-CS#7
  55         - GPIO13/CS4# -> CS4# USB HC or ISA emulation            ISA-CS#3
  56         - GPIO14/CS5# -> CS5# Boosted IDE access                 ISA-CS#4
  57         - GPIO15/CS6# -> CS6# ISA emulation                      ISA-CS#5
  58         - GPIO16/CS7# -> CS7# ISA emulation                      ISA-CS#6
  59         - GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line         ISA-IRQ#3
  60         - GPIO18/IRQ1 -> IRQ input                               ISA-IRQ#14
  61         - GPIO19/IRQ2 -> IRQ input or USB                        ISA-IRQ#4
  62         - GPIO20/IRQ3 -> IRQ input                               PCI-IRQ#D
  63         - GPIO21/IRQ4 -> IRQ input                               PCI-IRQ#C
  64         - GPIO22/IRQ5 -> IRQ input                               PCI-IRQ#B
  65         - GPIO23/IRQ6 -> IRQ input                               PCI-IRQ#A
  66         - GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
  67 */
  68 /*
  69 | CPLD register: io-space at offset 0x102 (write only)
  70 | 0
  71 | 1
  72 | 2 0=CS#4 USB CS#, 1=ISA or GP bus
  73 | 3
  74 | 4
  75 | 5
  76 | 6 1=enable faster IDE access
  77 | 7
  78 */
  79 #define USB_CHIP_ENABLE 0x04
  80 #define IDE_BOOSTING 0x40
  81
  82 /* --------------- USB stuff ------------------------------------- */
  83 #ifdef CONFIG_ISP1161_PRESENT
  84 /**
  85  * initUsbHost- Initialize the Philips isp1161 HC part if present
  86  * @cpldConfig: Pointer to value in write only CPLD register
  87  *
  88  * Initialize the USB host controller if present and fills the
  89  * scratch register to inform the driver about used resources
  90  */
  91
  92 static void initUsbHost (unsigned char *cpldConfig)
  93 {
  94         int i;
  95         unsigned long usbBase;
  96         /*
  97          * Read back where init.S has located the USB chip
  98          */
  99         mtdcr (0x012, 0x04);
 100         usbBase = mfdcr (0x013);
 101         if (!(usbBase & 0x18000))       /* enabled? */
 102                 return;
 103         usbBase &= 0xFFF00000;
 104
 105         /*
 106          * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
 107          */
 108         writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
 109
 110         /*
 111          * first check: is the controller assembled?
 112          */
 113         hcWriteWord (usbBase, 0x5555, HcScratch);
 114         if (hcReadWord (usbBase, HcScratch) == 0x5555) {
 115                 hcWriteWord (usbBase, 0xAAAA, HcScratch);
 116                 if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
 117                         if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
 118                                 return; /* this is not our controller */
 119                 /*
 120                  * try a software reset. This needs up to 10 seconds (see datasheet)
 121                  */
 122                         hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
 123                         for (i = 1000; i > 0; i--) {    /* loop up to 10 seconds */
 124                                 udelay (10);
 125                                 if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
 126                                         break;
 127                         }
 128
 129                         if (!i)
 130                                 return;  /* the controller doesn't responding. Broken? */
 131                 /*
 132                  * OK. USB controller is ready. Initialize it in such way the later driver
 133                  * can us it (without any knowing about specific implementation)
 134                  */
 135                         hcWriteDWord (usbBase, 0x00000000, HcControl);
 136                 /*
 137                  * disable all interrupt sources. Because we
 138                  * don't know where we come from (hard reset, cold start, soft reset...)
 139                  */
 140                         hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
 141                 /*
 142                  * our current setup hardware configuration
 143                  * - every port power supply can switched indepently
 144                  * - every port can signal overcurrent
 145                  * - every port is "outside" and the devices are removeable
 146                  */
 147                         hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
 148                         hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
 149                 /*
 150                  * don't forget to switch off power supply of each port
 151                  * The later running driver can reenable them to find and use
 152                  * the (maybe) connected devices.
 153                  *
 154                  */
 155                         hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
 156                         hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
 157                         hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
 158                         hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
 159                         hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
 160                         hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
 161                 /*
 162                  * controller is present and usable
 163                  */
 164                         *cpldConfig |= USB_CHIP_ENABLE;
 165                 }
 166         }
 167 }
 168 #endif
 169
 170 #if defined(CONFIG_START_IDE)
 171 int board_start_ide(void)
 172 {
 173         if (IS_CAMERON) {
 174                 puts ("no IDE on cameron board.\n");
 175                 return 0;
 176         }
 177         return 1;
 178 }
 179 #endif
 180
 181 static int sc3_cameron_init (void)
 182 {
 183         /* Set up the Memory Controller for the CAMERON version */
 184         mtebc (PB4AP, 0x01805940);
 185         mtebc (PB4CR, 0x7401a000);
 186         mtebc (PB5AP, 0x01805940);
 187         mtebc (PB5CR, 0x7401a000);
 188         mtebc (PB6AP, 0x0);
 189         mtebc (PB6CR, 0x0);
 190         mtebc (PB7AP, 0x0);
 191         mtebc (PB7CR, 0x0);
 192         return 0;
 193 }
 194
 195 void sc3_read_eeprom (void)
 196 {
 197         uchar i2c_buffer[18];
 198
 199         i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
 200         i2c_buffer[9] = 0;
 201         setenv ("serial#", (char *)i2c_buffer);
 202
 203         /* read mac-address from eeprom */
 204         i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
 205         i2c_buffer[17] = 0;
 206         i2c_buffer[16] = i2c_buffer[14];
 207         i2c_buffer[15] = i2c_buffer[13];
 208         i2c_buffer[14] = ':';
 209         i2c_buffer[13] = i2c_buffer[12];
 210         i2c_buffer[12] = i2c_buffer[11];
 211         i2c_buffer[11] = ':';
 212         i2c_buffer[8] = ':';
 213         i2c_buffer[5] = ':';
 214         i2c_buffer[2] = ':';
 215         setenv ("ethaddr", (char *)i2c_buffer);
 216 }
 217
 218 int board_early_init_f (void)
 219 {
 220         /* write only register to configure things in our CPLD */
 221         unsigned char cpldConfig_1=0x00;
 222
 223 /*-------------------------------------------------------------------------+
 224 | Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
 225 |
 226 | Note: IRQ 0  UART 0, active high; level sensitive
 227 |       IRQ 1  UART 1, active high; level sensitive
 228 |       IRQ 2  IIC, active high; level sensitive
 229 |       IRQ 3  Ext. master, rising edge, edge sensitive
 230 |       IRQ 4  PCI, active high; level sensitive
 231 |       IRQ 5  DMA Channel 0, active high; level sensitive
 232 |       IRQ 6  DMA Channel 1, active high; level sensitive
 233 |       IRQ 7  DMA Channel 2, active high; level sensitive
 234 |       IRQ 8  DMA Channel 3, active high; level sensitive
 235 |       IRQ 9  Ethernet Wakeup, active high; level sensitive
 236 |       IRQ 10 MAL System Error (SERR), active high; level sensitive
 237 |       IRQ 11 MAL Tx End of Buffer, active high; level sensitive
 238 |       IRQ 12 MAL Rx End of Buffer, active high; level sensitive
 239 |       IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
 240 |       IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
 241 |       IRQ 15 Ethernet, active high; level sensitive
 242 |       IRQ 16 External PCI SERR, active high; level sensitive
 243 |       IRQ 17 ECC Correctable Error, active high; level sensitive
 244 |       IRQ 18 PCI Power Management, active high; level sensitive
 245 |
 246 |       IRQ 19 (EXT IRQ7 405GPr only)
 247 |       IRQ 20 (EXT IRQ8 405GPr only)
 248 |       IRQ 21 (EXT IRQ9 405GPr only)
 249 |       IRQ 22 (EXT IRQ10 405GPr only)
 250 |       IRQ 23 (EXT IRQ11 405GPr only)
 251 |       IRQ 24 (EXT IRQ12 405GPr only)
 252 |
 253 |       IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
 254 |       IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
 255 |       IRQ 27 (EXT IRQ 2) USB controller
 256 |       IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
 257 |       IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
 258 |       IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
 259 |       IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
 260 |
 261 | Direct Memory Access Controller Signal Polarities
 262 |       DRQ0 active high (like ISA)
 263 |       ACK0 active low (like ISA)
 264 |       EOT0 active high (like ISA)
 265 |       DRQ1 active high (like ISA)
 266 |       ACK1 active low (like ISA)
 267 |       EOT1 active high (like ISA)
 268 |       DRQ2 active high (like ISA)
 269 |       ACK2 active low (like ISA)
 270 |       EOT2 active high (like ISA)
 271 |       DRQ3 active high (like ISA)
 272 |       ACK3 active low (like ISA)
 273 |       EOT3 active high (like ISA)
 274 |
 275 +-------------------------------------------------------------------------*/
 276
 277         writeb (cpldConfig_1, CPLD_CONTROL_1);  /* disable everything in CPLD */
 278
 279         mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
 280         mtdcr (UIC0ER, 0x00000000);    /* disable all ints */
 281         mtdcr (UIC0CR, 0x00000000);    /* set all to be non-critical */
 282
 283         if (IS_CAMERON) {
 284                 sc3_cameron_init();
 285                 mtdcr (0x0B6, 0x18000000);
 286                 mtdcr (UIC0PR, 0xFFFFFFF0);
 287                 mtdcr (UIC0TR, 0x10001030);
 288         } else {
 289                 mtdcr (0x0B6, 0x0000000);
 290                 mtdcr (UIC0PR, 0xFFFFFFE0);
 291                 mtdcr (UIC0TR, 0x10000020);
 292         }
 293         mtdcr (UIC0VCR, 0x00000001);   /* set vect base=0,INT0 highest priority */
 294         mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
 295
 296         /* setup other implementation specific details */
 297         mtdcr (CPC0_ECR, 0x60606000);
 298
 299         mtdcr (CPC0_CR1, 0x000042C0);
 300
 301         if (IS_CAMERON) {
 302                 mtdcr (CPC0_CR0, 0x01380000);
 303                 /* Setup the GPIOs */
 304                 writel (0x08008000, 0xEF600700);        /* Output states */
 305                 writel (0x00000000, 0xEF600718);        /* Open Drain control */
 306                 writel (0x68098000, 0xEF600704);        /* Output control */
 307         } else {
 308                 mtdcr (CPC0_CR0,0x00080000);
 309                 /* Setup the GPIOs */
 310                 writel (0x08000000, 0xEF600700);        /* Output states */
 311                 writel (0x14000000, 0xEF600718);        /* Open Drain control */
 312                 writel (0x7C000000, 0xEF600704);        /* Output control */
 313         }
 314
 315         /* Code decompression disabled */
 316         mtdcr (DCP0_CFGADDR, KCONF);
 317         mtdcr (DCP0_CFGDATA, 0x2B);
 318
 319         /* CPC0_ER: enable sleep mode of (currently) unused components */
 320         /* CPC0_FR: force unused components into sleep mode */
 321         mtdcr (CPC0_ER, 0x3F800000);
 322         mtdcr (CPC0_FR, 0x14000000);
 323
 324         /* set PLB priority */
 325         mtdcr (PLB0_ACR, 0x08000000);
 326
 327         /* --------------- DMA stuff ------------------------------------- */
 328         mtdcr (0x126, 0x49200000);
 329
 330 #ifndef IDE_USES_ISA_EMULATION
 331         cpldConfig_1 |= IDE_BOOSTING;   /* enable faster IDE */
 332         /* cpldConfig |= 0x01; */       /* enable 8.33MHz output, if *not* present on your baseboard */
 333         writeb (cpldConfig_1, CPLD_CONTROL_1);
 334 #endif
 335
 336 #ifdef CONFIG_ISP1161_PRESENT
 337         initUsbHost (&cpldConfig_1);
 338         writeb (cpldConfig_1, CPLD_CONTROL_1);
 339 #endif
 340         /* FIXME: for what must we do this */
 341         *(unsigned long *)0x79000080 = 0x0001;
 342         return(0);
 343 }
 344
 345 int misc_init_r (void)
 346 {
 347         char *s1;
 348         int i, xilinx_val;
 349         volatile char *xilinx_adr;
 350         xilinx_adr = (char *)0x79000102;
 351
 352         *xilinx_adr = 0x00;
 353
 354 /* customer settings ***************************************** */
 355 /*
 356         s1 = getenv ("function");
 357         if (s1) {
 358                 if (!strcmp (s1, "Rosho")) {
 359                         printf ("function 'Rosho' activated\n");
 360                         *xilinx_adr = 0x40;
 361                 }
 362                 else {
 363                         printf (">>>>>>>>>> function %s not recognized\n",s1);
 364                 }
 365         }
 366 */
 367
 368 /* individual settings ***************************************** */
 369         if ((s1 = getenv ("xilinx"))) {
 370                 i=0;
 371                 xilinx_val = 0;
 372                 while (i < 3 && s1[i]) {
 373                         if (s1[i] >= '0' && s1[i] <= '9')
 374                                 xilinx_val = (xilinx_val << 4) + s1[i] - '0';
 375                         else
 376                                 if (s1[i] >= 'A' && s1[i] <= 'F')
 377                                         xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
 378                                 else
 379                                         if (s1[i] >= 'a' && s1[i] <= 'f')
 380                                                 xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
 381                                         else {
 382                                                 xilinx_val = -1;
 383                                                 break;
 384                                         }
 385                         i++;
 386                 }
 387                 if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
 388                         printf ("Xilinx: set to %s\n", s1);
 389                         *xilinx_adr = (unsigned char) xilinx_val;
 390                 } else
 391                         printf ("Xilinx: rejected value %s\n", s1);
 392         }
 393         return 0;
 394 }
 395
 396 /* -------------------------------------------------------------------------
 397  * printCSConfig
 398  *
 399  * Print some informations about chips select configurations
 400  * Only used while debugging.
 401  *
 402  * Params:
 403  * - No. of CS pin
 404  * - AP of this CS
 405  * - CR of this CS
 406  *
 407  * Returns
 408  * nothing
 409    ------------------------------------------------------------------------- */
 410
 411 #ifdef SC3_DEBUGOUT
 412 static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
 413 {
 414         const char *bsize[4] = {"8","16","32","?"};
 415         const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
 416         const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
 417
 418 #define CYCLE 30  /* time of one clock (based on 33MHz) */
 419
 420         printf("\nCS#%d",reg);
 421         if (!(cr & 0x00018000))
 422                 puts(" unused");
 423         else {
 424                 if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
 425                         puts(" Address is not multiple of bank size!");
 426
 427                 printf("\n -%s bit device",
 428                         bsize[(cr & 0x00006000) >> 13]);
 429                 printf(" at 0x%08lX", cr & 0xFFF00000U);
 430                 printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
 431                 printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
 432                 if (ap & 0x80000000) {
 433                         printf("\n -Burst device (%luns/%luns)",
 434                                 (((ap & 0x7C000000) >> 26) + 1) * CYCLE,
 435                                 (((ap & 0x03800000) >> 23) + 1) * CYCLE);
 436                 } else {
 437                         printf("\n -Non burst device, active cycle %luns",
 438                                 (((ap & 0x7F800000) >> 23) + 1) * CYCLE);
 439                         printf("\n -Address setup %luns",
 440                                 ((ap & 0xC0000) >> 18) * CYCLE);
 441                         printf("\n -CS active to RD %luns/WR %luns",
 442                                 ((ap & 0x30000) >> 16) * CYCLE,
 443                                 ((ap & 0xC000) >> 14) * CYCLE);
 444                         printf("\n -WR to CS inactive %luns",
 445                                 ((ap & 0x3000) >> 12) * CYCLE);
 446                         printf("\n -Hold after access %luns",
 447                                 ((ap & 0xE00) >> 9) * CYCLE);
 448                         printf("\n -Ready is %sabled",
 449                                 ap & 0x100 ? "en" : "dis");
 450                 }
 451         }
 452 }
 453 #endif
 454
 455 #ifdef SC3_DEBUGOUT
 456
 457 static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP,
 458                                 PB5AP, PB6AP, PB7AP};
 459 static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR,
 460                                 PB5CR, PB6CR, PB7CR};
 461
 462 static int show_reg (int nr)
 463 {
 464         unsigned long ul1, ul2;
 465
 466         mtdcr (EBC0_CFGADDR, ap[nr]);
 467         ul1 = mfdcr (EBC0_CFGDATA);
 468         mtdcr (EBC0_CFGADDR, cr[nr]);
 469         ul2 = mfdcr(EBC0_CFGDATA);
 470         printCSConfig(nr, ul1, ul2);
 471         return 0;
 472 }
 473 #endif
 474
 475 int checkboard (void)
 476 {
 477 #ifdef SC3_DEBUGOUT
 478         unsigned long ul1;
 479         int     i;
 480
 481         for (i = 0; i < 8; i++) {
 482                 show_reg (i);
 483         }
 484
 485         mtdcr (EBC0_CFGADDR, EBC0_CFG);
 486         ul1 = mfdcr (EBC0_CFGDATA);
 487
 488         puts ("\nGeneral configuration:\n");
 489
 490         if (ul1 & 0x80000000)
 491                 printf(" -External Bus is always driven\n");
 492
 493         if (ul1 & 0x400000)
 494                 printf(" -CS signals are always driven\n");
 495
 496         if (ul1 & 0x20000)
 497                 printf(" -PowerDown after %lu clocks\n",
 498                         (ul1 & 0x1F000) >> 7);
 499
 500         switch (ul1 & 0xC0000)
 501         {
 502         case 0xC0000:
 503                 printf(" -No external master present\n");
 504                 break;
 505         case 0x00000:
 506                 printf(" -8 bit external master present\n");
 507                 break;
 508         case 0x40000:
 509                 printf(" -16 bit external master present\n");
 510                 break;
 511         case 0x80000:
 512                 printf(" -32 bit external master present\n");
 513                 break;
 514         }
 515
 516         switch (ul1 & 0x300000)
 517         {
 518         case 0x300000:
 519                 printf(" -Prefetch: Illegal setting!\n");
 520                 break;
 521         case 0x000000:
 522                 printf(" -1 doubleword prefetch\n");
 523                 break;
 524         case 0x100000:
 525                 printf(" -2 doublewords prefetch\n");
 526                 break;
 527         case 0x200000:
 528                 printf(" -4 doublewords prefetch\n");
 529                 break;
 530         }
 531         putc ('\n');
 532 #endif
 533         printf("Board: SolidCard III %s %s version.\n",
 534                 (IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
 535         return 0;
 536 }
 537
 538 static int printSDRAMConfig(char reg, unsigned long cr)
 539 {
 540         const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
 541 #ifdef SC3_DEBUGOUT
 542         const char *basize[8]=
 543                 {"4", "8", "16", "32", "64", "128", "256", "Reserved"};
 544
 545         printf("SDRAM bank %d",reg);
 546
 547         if (!(cr & 0x01))
 548                 puts(" disabled\n");
 549         else {
 550                 printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
 551                 printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
 552         }
 553 #endif
 554
 555         if (cr & 0x01)
 556                 return(bisize[(cr & 0xE0000) >> 17]);
 557
 558         return 0;
 559 }
 560
 561 #ifdef SC3_DEBUGOUT
 562 static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
 563 #endif
 564
 565 phys_size_t initdram (int board_type)
 566 {
 567         unsigned int mems=0;
 568         unsigned long ul1;
 569
 570 #ifdef SC3_DEBUGOUT
 571         unsigned long ul2;
 572         int     i;
 573
 574         puts("\nSDRAM configuration:\n");
 575
 576         mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
 577         ul1 = mfdcr(SDRAM0_CFGDATA);
 578
 579         if (!(ul1 & 0x80000000)) {
 580                 puts(" Controller disabled\n");
 581                 return 0;
 582         }
 583         for (i = 0; i < 4; i++) {
 584                 mtdcr (SDRAM0_CFGADDR, mbcf[i]);
 585                 ul1 = mfdcr (SDRAM0_CFGDATA);
 586                 mems += printSDRAMConfig (i, ul1);
 587         }
 588
 589         mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
 590         ul1 = mfdcr(SDRAM0_CFGDATA);
 591
 592         printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
 593         printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
 594         printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
 595         printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
 596         printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
 597         printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
 598         puts ("Misc:\n");
 599         mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
 600         ul1 = mfdcr(SDRAM0_CFGDATA);
 601         printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
 602
 603         mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
 604         ul2=mfdcr(SDRAM0_CFGDATA);
 605
 606         mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
 607         ul1=mfdcr(SDRAM0_CFGDATA);
 608
 609         if (ul1 & 0x20000000)
 610                 printf(" -Power Down after: %luns\n",
 611                         ((ul2 & 0xFFC00000) >> 22) * 7);
 612         else
 613                 puts(" -Power Down disabled\n");
 614
 615         if (ul1 & 0x40000000)
 616                 printf(" -Self refresh feature active\n");
 617         else
 618                 puts(" -Self refresh disabled\n");
 619
 620         if (ul1 & 0x10000000)
 621                 puts(" -ECC enabled\n");
 622         else
 623                 puts(" -ECC disabled\n");
 624
 625         if (ul1 & 0x8000000)
 626                 puts(" -Using registered SDRAM\n");
 627
 628         if (!(ul1 & 0x6000000))
 629                 puts(" -Using 32 bit data width\n");
 630         else
 631                 puts(" -Illegal data width!\n");
 632
 633         if (ul1 & 0x400000)
 634                 puts(" -ECC drivers inactive\n");
 635         else
 636                 puts(" -ECC drivers active\n");
 637
 638         if (ul1 & 0x200000)
 639                 puts(" -Memory lines always active outputs\n");
 640         else
 641                 puts(" -Memory lines only at write cycles active outputs\n");
 642
 643         mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
 644         ul1 = mfdcr (SDRAM0_CFGDATA);
 645         if (ul1 & 0x80000000)
 646                 puts(" -SDRAM Controller ready\n");
 647         else
 648                 puts(" -SDRAM Controller not ready\n");
 649
 650         if (ul1 & 0x4000000)
 651                 puts(" -SDRAM in self refresh mode!\n");
 652
 653         return (mems * 1024 * 1024);
 654 #else
 655         mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 656         ul1 = mfdcr (SDRAM0_CFGDATA);
 657         mems = printSDRAMConfig (0, ul1);
 658
 659         mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 660         ul1 = mfdcr (SDRAM0_CFGDATA);
 661         mems += printSDRAMConfig (1, ul1);
 662
 663         mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 664         ul1 = mfdcr(SDRAM0_CFGDATA);
 665         mems += printSDRAMConfig (2, ul1);
 666
 667         mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 668         ul1 = mfdcr(SDRAM0_CFGDATA);
 669         mems += printSDRAMConfig (3, ul1);
 670
 671         return (mems * 1024 * 1024);
 672 #endif
 673 }
 674
 675 static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 676 {
 677 /*-------------------------------------------------------------------------+
 678  |             ,-.     ,-.        ,-.        ,-.        ,-.
 679  |   INTD# ----|B|-----|P|-.    ,-|P|-.    ,-| |-.    ,-|G|
 680  |             |R|     |C|  \  /  |C|  \  /  |E|  \  /  |r|
 681  |   INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
 682  |             |D|     |0|  \/    |0|  \/    |h|  \/    |f|
 683  |   INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
 684  |             |E|     |+| /\     |+| /\     |r| /\     |k|
 685  |   INTA# ----| |-----| |-  `----| |-  `----| |-  `----| |
 686  |             `-'     `-'        `-'        `-'        `-'
 687  |   Slot      0       10         11         12         13
 688  |   REQ#              0          1          2          *
 689  |   GNT#              0          1          2          *
 690  +-------------------------------------------------------------------------*/
 691         unsigned char int_line = 0xff;
 692
 693         switch (PCI_DEV(dev)) {
 694         case 10:
 695                 int_line = 31; /* INT A */
 696                 POST_OUT(0x42);
 697                 break;
 698
 699         case 11:
 700                 int_line = 30; /* INT B */
 701                 POST_OUT(0x43);
 702                 break;
 703
 704         case 12:
 705                 int_line = 29; /* INT C */
 706                 POST_OUT(0x44);
 707                 break;
 708
 709         case 13:
 710                 int_line = 28; /* INT D */
 711                 POST_OUT(0x45);
 712                 break;
 713         }
 714         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 715 }
 716
 717 extern void pci_405gp_init(struct pci_controller *hose);
 718 extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
 719 extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
 720 /*
 721  * The following table is used when there is a special need to setup a PCI device.
 722  * For every PCI device found in this table is called the given init function with given
 723  * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
 724  * parameters!
 725  *
 726 */
 727 static struct pci_config_table pci_solidcard3_config_table[] =
 728 {
 729 /* Host to PCI Bridge device (405GP) */
 730         {
 731                 vendor: 0x1014,
 732                 device: 0x0156,
 733                 class: PCI_CLASS_BRIDGE_HOST,
 734                 bus: 0,
 735                 dev: 0,
 736                 func: 0,
 737                 config_device: pci_405gp_setup_bridge
 738         },
 739         { }
 740 };
 741
 742 /*-------------------------------------------------------------------------+
 743  | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
 744  |
 745  | Init the PCI part of the SolidCard III
 746  |
 747  | Params:
 748  * - Pointer to current PCI hose
 749  * - Current Device
 750  *
 751  * Returns
 752  * nothing
 753  +-------------------------------------------------------------------------*/
 754
 755 void pci_init_board(void)
 756 {
 757         POST_OUT(0x41);
 758 /*
 759  * we want the ptrs to RAM not flash (ie don't use init list)
 760  */
 761         hose.fixup_irq    = pci_solidcard3_fixup_irq;
 762         hose.config_table = pci_solidcard3_config_table;
 763         pci_405gp_init(&hose);
 764 }
 765
 766 int board_eth_init(bd_t *bis)
 767 {
 768         return pci_eth_init(bis);
 769 }