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1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /**
9 * hcWriteWord - write a 16 bit value into the USB controller
10 * @base: base address to access the chip registers
11 * @value: 16 bit value to write into register @offset
12 * @offset: register to write the @value into
13 *
14 */
15 static void inline hcWriteWord (unsigned long base, unsigned int value,
16 unsigned int offset)
17 {
18 out_le16 ((volatile u16*)(base + 2), offset | 0x80);
19 out_le16 ((volatile u16*)base, value);
20 }
21
22 /**
23 * hcWriteDWord - write a 32 bit value into the USB controller
24 * @base: base address to access the chip registers
25 * @value: 32 bit value to write into register @offset
26 * @offset: register to write the @value into
27 *
28 */
29
30 static void inline hcWriteDWord (unsigned long base, unsigned long value,
31 unsigned int offset)
32 {
33 out_le16 ((volatile u16*)(base + 2), offset | 0x80);
34 out_le16 ((volatile u16*)base, value);
35 out_le16 ((volatile u16*)base, value >> 16);
36 }
37
38 /**
39 * hcReadWord - read a 16 bit value from the USB controller
40 * @base: base address to access the chip registers
41 * @offset: register to read from
42 *
43 * Returns the readed register value
44 */
45
46 static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
47 {
48 out_le16 ((volatile u16*)(base + 2), offset);
49 return (in_le16 ((volatile u16*)base));
50 }
51
52 /**
53 * hcReadDWord - read a 32 bit value from the USB controller
54 * @base: base address to access the chip registers
55 * @offset: register to read from
56 *
57 * Returns the readed register value
58 */
59
60 static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
61 {
62 unsigned long val, val16;
63
64 out_le16 ((volatile u16*)(base + 2), offset);
65 val = in_le16((volatile u16*)base);
66 val16 = in_le16((volatile u16*)base);
67 return (val | (val16 << 16));
68 }
69
70 /* control and status registers isp1161 */
71 #define HcRevision 0x00
72 #define HcControl 0x01
73 #define HcCommandStatus 0x02
74 #define HcInterruptStatus 0x03
75 #define HcInterruptEnable 0x04
76 #define HcInterruptDisable 0x05
77 #define HcFmInterval 0x0D
78 #define HcFmRemaining 0x0E
79 #define HcFmNumber 0x0F
80 #define HcLSThreshold 0x11
81 #define HcRhDescriptorA 0x12
82 #define HcRhDescriptorB 0x13
83 #define HcRhStatus 0x14
84 #define HcRhPortStatus1 0x15
85 #define HcRhPortStatus2 0x16
86
87 #define HcHardwareConfiguration 0x20
88 #define HcDMAConfiguration 0x21
89 #define HcTransferCounter 0x22
90 #define HcuPInterrupt 0x24
91 #define HcuPInterruptEnable 0x25
92 #define HcChipID 0x27
93 #define HcScratch 0x28
94 #define HcSoftwareReset 0x29
95 #define HcITLBufferLength 0x2A
96 #define HcATLBufferLength 0x2B
97 #define HcBufferStatus 0x2C
98 #define HcReadBackITL0Length 0x2D
99 #define HcReadBackITL1Length 0x2E
100 #define HcITLBufferPort 0x40
101 #define HcATLBufferPort 0x41