board/sc520_cdp/sc520_cdp.c

   1 /*
   2  *
   3  * (C) Copyright 2002
   4  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <asm/io.h>
  28 #include <asm/pci.h>
  29 #include <asm/ic/sc520.h>
  30 #include <asm/ic/ali512x.h>
  31 #include <spi.h>
  32 #include <netdev.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #undef SC520_CDP_DEBUG
  37
  38 #ifdef  SC520_CDP_DEBUG
  39 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  40 #else
  41 #define PRINTF(fmt,args...)
  42 #endif
  43
  44 /* ------------------------------------------------------------------------- */
  45
  46
  47 /*
  48  * Theory:
  49  * We first set up all IRQs to be non-pci, edge triggered,
  50  * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
  51  * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
  52  * as needed. Whe choose the irqs to gram from a configurable list
  53  * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
  54  * such as 0 thngas will not work)
  55  */
  56
  57 static void irq_init(void)
  58 {
  59         /* disable global interrupt mode */
  60         write_mmcr_byte(SC520_PICICR, 0x40);
  61
  62         /* set all irqs to edge */
  63         write_mmcr_byte(SC520_MPICMODE, 0x00);
  64         write_mmcr_byte(SC520_SL1PICMODE, 0x00);
  65         write_mmcr_byte(SC520_SL2PICMODE, 0x00);
  66
  67         /* active low polarity on PIC interrupt pins,
  68          *  active high polarity on all other irq pins */
  69         write_mmcr_word(SC520_INTPINPOL, 0x0000);
  70
  71         /* set irq number mapping */
  72         write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
  73         write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
  74         write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
  75         write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
  76         write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
  77         write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
  78         write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
  79         write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
  80         write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
  81         write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
  82         write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
  83         write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED);      /* disable Synchronius serial INT */
  84         write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
  85         write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
  86         write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
  87         write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
  88         write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
  89
  90         if (CONFIG_SYS_USE_SIO_UART) {
  91                 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
  92                 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
  93                 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
  94                 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4);          /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
  95         } else {
  96                 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);         /* Set internal UART2 INT to IRQ4 */
  97                 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);         /* Set internal UART2 INT to IRQ3 */
  98                 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ3 (ISA IRQ3) */
  99                 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ4 (ISA IRQ4) */
 100         }
 101
 102         write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1);             /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
 103         write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
 104         write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
 105         write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
 106         write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8);             /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
 107         write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9);             /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
 108         write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11);            /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
 109         write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12);            /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
 110         write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14);            /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
 111
 112         write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);                /* Map PCI hostbridge INT to NMI */
 113         write_mmcr_word(SC520_ECCMAP, 0x100);                    /* Map SDRAM ECC failure INT to NMI */
 114
 115 }
 116
 117 #ifdef CONFIG_PCI
 118 /* PCI stuff */
 119 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 120 {
 121         /* a configurable lists of irqs to steal
 122          * when we need one (a board with more pci interrupt pins
 123          * would use a larger table */
 124         static int irq_list[] = {
 125                 CONFIG_SYS_FIRST_PCI_IRQ,
 126                 CONFIG_SYS_SECOND_PCI_IRQ,
 127                 CONFIG_SYS_THIRD_PCI_IRQ,
 128                 CONFIG_SYS_FORTH_PCI_IRQ
 129         };
 130         static int next_irq_index=0;
 131
 132         uchar tmp_pin;
 133         int pin;
 134
 135         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
 136         pin = tmp_pin;
 137
 138         pin-=1; /* pci config space use 1-based numbering */
 139         if (-1 == pin) {
 140                 return; /* device use no irq */
 141         }
 142
 143
 144         /* map device number +  pin to a pin on the sc520 */
 145         switch (PCI_DEV(dev)) {
 146         case 20:
 147                 pin+=SC520_PCI_INTA;
 148                 break;
 149
 150         case 19:
 151                 pin+=SC520_PCI_INTB;
 152                 break;
 153
 154         case 18:
 155                 pin+=SC520_PCI_INTC;
 156                 break;
 157
 158         case 17:
 159                 pin+=SC520_PCI_INTD;
 160                 break;
 161
 162         default:
 163                 return;
 164         }
 165
 166         pin&=3; /* wrap around */
 167
 168         if (sc520_pci_ints[pin] == -1) {
 169                 /* re-route one interrupt for us */
 170                 if (next_irq_index > 3) {
 171                         return;
 172                 }
 173                 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
 174                         return;
 175                 }
 176                 next_irq_index++;
 177         }
 178
 179
 180         if (-1 != sc520_pci_ints[pin]) {
 181                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 182                                            sc520_pci_ints[pin]);
 183         }
 184         PRINTF("fixup_irq: device %d pin %c irq %d\n",
 185                PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
 186 }
 187
 188 static struct pci_controller sc520_cdp_hose = {
 189         fixup_irq: pci_sc520_cdp_fixup_irq,
 190 };
 191
 192 void pci_init_board(void)
 193 {
 194         pci_sc520_init(&sc520_cdp_hose);
 195 }
 196 #endif
 197
 198 static void silence_uart(int port)
 199 {
 200         outb(0, port+1);
 201 }
 202
 203 void setup_ali_sio(int uart_primary)
 204 {
 205         ali512x_init();
 206
 207         ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
 208         ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
 209         ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
 210         ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
 211         ali512x_set_rtc(ALI_DISABLED, 0, 0);
 212         ali512x_set_kbc(ALI_ENABLED, 1, 12);
 213         ali512x_set_cio(ALI_ENABLED);
 214
 215         /* IrDa pins */
 216         ali512x_cio_function(12, 1, 0, 0);
 217         ali512x_cio_function(13, 1, 0, 0);
 218
 219         /* SSI chip select pins */
 220         ali512x_cio_function(14, 0, 0, 0);  /* SSI_CS */
 221         ali512x_cio_function(15, 0, 0, 0);  /* SSI_MV */
 222         ali512x_cio_function(16, 0, 0, 0);  /* SSI_SPI# */
 223
 224         /* Board REV pins */
 225         ali512x_cio_function(20, 0, 0, 1);
 226         ali512x_cio_function(21, 0, 0, 1);
 227         ali512x_cio_function(22, 0, 0, 1);
 228         ali512x_cio_function(23, 0, 0, 1);
 229 }
 230
 231
 232 /* set up the ISA bus timing and system address mappings */
 233 static void bus_init(void)
 234 {
 235
 236         /* set up the GP IO pins */
 237         write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff);     /* set the GPIO pin function 31-16 reg */
 238         write_mmcr_word(SC520_PIOPFS15_0, 0xffff);      /* set the GPIO pin function 15-0 reg */
 239         write_mmcr_byte(SC520_CSPFS, 0xf8);             /* set the CS pin function  reg */
 240         write_mmcr_byte(SC520_CLKSEL, 0x70);
 241
 242
 243         write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
 244         write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
 245         write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
 246         write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
 247         write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
 248         write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
 249         write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
 250
 251         write_mmcr_word(SC520_BOOTCSCTL, 0x1823);               /* set up timing of BOOTCS */
 252         write_mmcr_word(SC520_ROMCS1CTL, 0x1823);               /* set up timing of ROMCS1 */
 253         write_mmcr_word(SC520_ROMCS2CTL, 0x1823);               /* set up timing of ROMCS2 */
 254
 255         /* adjust the memory map:
 256          * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
 257          * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
 258          * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
 259
 260
 261         /* SRAM = GPCS3 128k @ d0000-effff*/
 262         write_mmcr_long(SC520_PAR2,  0x4e00400d);
 263
 264         /* IDE0 = GPCS6 1f0-1f7 */
 265         write_mmcr_long(SC520_PAR3,  0x380801f0);
 266
 267         /* IDE1 = GPCS7 3f6 */
 268         write_mmcr_long(SC520_PAR4,  0x3c0003f6);
 269         /* bootcs */
 270         write_mmcr_long(SC520_PAR12, 0x8bffe800);
 271         /* romcs2 */
 272         write_mmcr_long(SC520_PAR13, 0xcbfff000);
 273         /* romcs1 */
 274         write_mmcr_long(SC520_PAR14, 0xabfff800);
 275         /* 680 LEDS */
 276         write_mmcr_long(SC520_PAR15, 0x30000640);
 277
 278         write_mmcr_byte(SC520_ADDDECCTL, 0);
 279
 280         asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 281
 282         if (CONFIG_SYS_USE_SIO_UART) {
 283                 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
 284                 setup_ali_sio(1);
 285         } else {
 286                 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
 287                 setup_ali_sio(0);
 288                 silence_uart(0x3e8);
 289                 silence_uart(0x2e8);
 290         }
 291
 292 }
 293
 294 /* GPCS usage
 295  * GPCS0       PIO27 (NMI)
 296  * GPCS1       ROMCS1
 297  * GPCS2       ROMCS2
 298  * GPCS3       SRAMCS       PAR2
 299  * GPCS4       unused       PAR3
 300  * GPCS5       unused       PAR4
 301  * GPCS6       IDE
 302  * GPCS7       IDE
 303  */
 304
 305
 306 /* par usage:
 307  * PAR0   legacy_video
 308  * PAR1   PCI ROM mapping
 309  * PAR2   SRAM
 310  * PAR3   IDE
 311  * PAR4   IDE
 312  * PAR5   legacy_video
 313  * PAR6   legacy_video
 314  * PAR7   legacy_video
 315  * PAR8   legacy_video
 316  * PAR9   legacy_video
 317  * PAR10  legacy_video
 318  * PAR11  ISAROM
 319  * PAR12  BOOTCS
 320  * PAR13  ROMCS1
 321  * PAR14  ROMCS2
 322  * PAR15  Port 0x680 LED display
 323  */
 324
 325 /*
 326  * This function should map a chunk of size bytes
 327  * of the system address space to the ISA bus
 328  *
 329  * The function will return the memory address
 330  * as seen by the host (which may very will be the
 331  * same as the bus address)
 332  */
 333 u32 isa_map_rom(u32 bus_addr, int size)
 334 {
 335         u32 par;
 336
 337         PRINTF("isa_map_rom asked to map %d bytes at %x\n",
 338                size, bus_addr);
 339
 340         par = size;
 341         if (par < 0x80000) {
 342                 par = 0x80000;
 343         }
 344         par >>= 12;
 345         par--;
 346         par&=0x7f;
 347         par <<= 18;
 348         par |= (bus_addr>>12);
 349         par |= 0x50000000;
 350
 351         PRINTF ("setting PAR11 to %x\n", par);
 352
 353         /* Map rom 0x10000 with PAR1 */
 354         write_mmcr_long(SC520_PAR11,  par);
 355
 356         return bus_addr;
 357 }
 358
 359 /*
 360  * this function removed any mapping created
 361  * with pci_get_rom_window()
 362  */
 363 void isa_unmap_rom(u32 addr)
 364 {
 365         PRINTF("isa_unmap_rom asked to unmap %x", addr);
 366         if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
 367                 write_mmcr_long(SC520_PAR11, 0);
 368                 PRINTF(" done\n");
 369                 return;
 370         }
 371         PRINTF(" not ours\n");
 372 }
 373
 374 #ifdef CONFIG_PCI
 375 #define PCI_ROM_TEMP_SPACE 0x10000
 376 /*
 377  * This function should map a chunk of size bytes
 378  * of the system address space to the PCI bus,
 379  * suitable to map PCI ROMS (bus address < 16M)
 380  * the function will return the host memory address
 381  * which should be converted into a bus address
 382  * before used to configure the PCI rom address
 383  * decoder
 384  */
 385 u32 pci_get_rom_window(struct pci_controller *hose, int size)
 386 {
 387         u32 par;
 388
 389         par = size;
 390         if (par < 0x80000) {
 391                 par = 0x80000;
 392         }
 393         par >>= 16;
 394         par--;
 395         par&=0x7ff;
 396         par <<= 14;
 397         par |= (PCI_ROM_TEMP_SPACE>>16);
 398         par |= 0x72000000;
 399
 400         PRINTF ("setting PAR1 to %x\n", par);
 401
 402         /* Map rom 0x10000 with PAR1 */
 403         write_mmcr_long(SC520_PAR1,  par);
 404
 405         return PCI_ROM_TEMP_SPACE;
 406 }
 407
 408 /*
 409  * this function removed any mapping created
 410  * with pci_get_rom_window()
 411  */
 412 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 413 {
 414         PRINTF("pci_remove_rom_window: %x", addr);
 415         if (addr == PCI_ROM_TEMP_SPACE) {
 416                 write_mmcr_long(SC520_PAR1, 0);
 417                 PRINTF(" done\n");
 418                 return;
 419         }
 420         PRINTF(" not ours\n");
 421
 422 }
 423
 424 /*
 425  * This function is called in order to provide acces to the
 426  * legacy video I/O ports on the PCI bus.
 427  * After this function accesses to I/O ports 0x3b0-0x3bb and
 428  * 0x3c0-0x3df shuld result in transactions on the PCI bus.
 429  *
 430  */
 431 int pci_enable_legacy_video_ports(struct pci_controller *hose)
 432 {
 433         /* Map video memory to 0xa0000*/
 434         write_mmcr_long(SC520_PAR0,  0x7200400a);
 435
 436         /* forward all I/O accesses to PCI */
 437         write_mmcr_byte(SC520_ADDDECCTL,
 438                         read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
 439
 440
 441         /* so we map away all io ports to pci (only way to access pci io
 442          * below 0x400. But then we have to map back the portions that we dont
 443          * use so that the generate cycles on the GPIO bus where the sio and
 444          * ISA slots are connected, this requre the use of several PAR registers
 445          */
 446
 447         /* bring 0x100 - 0x1ef back to ISA using PAR5 */
 448         write_mmcr_long(SC520_PAR5, 0x30ef0100);
 449
 450         /* IDE use 1f0-1f7 */
 451
 452         /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
 453         write_mmcr_long(SC520_PAR6, 0x30ff01f8);
 454
 455         /* com2 use 2f8-2ff */
 456
 457         /* bring 0x300 - 0x3af back to ISA using PAR7 */
 458         write_mmcr_long(SC520_PAR7, 0x30af0300);
 459
 460         /* vga use 3b0-3bb */
 461
 462         /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
 463         write_mmcr_long(SC520_PAR8, 0x300303bc);
 464
 465         /* vga use 3c0-3df */
 466
 467         /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
 468         write_mmcr_long(SC520_PAR9, 0x301503e0);
 469
 470         /* ide use 3f6 */
 471
 472         /* bring 0x3f7  back to ISA using PAR10 */
 473         write_mmcr_long(SC520_PAR10, 0x300003f7);
 474
 475         /* com1 use 3f8-3ff */
 476
 477         return 0;
 478 }
 479 #endif
 480
 481 /*
 482  * Miscelaneous platform dependent initialisations
 483  */
 484
 485 int board_init(void)
 486 {
 487         init_sc520();
 488         bus_init();
 489         irq_init();
 490
 491         /* max drive current on SDRAM */
 492         write_mmcr_word(SC520_DSCTL, 0x0100);
 493
 494         /* enter debug mode after next reset (only if jumper is also set) */
 495         write_mmcr_byte(SC520_RESCFG, 0x08);
 496         /* configure the software timer to 33.333MHz */
 497         write_mmcr_byte(SC520_SWTMRCFG, 0);
 498         gd->bus_clk = 33333000;
 499
 500         return 0;
 501 }
 502
 503 int dram_init(void)
 504 {
 505         init_sc520_dram();
 506         return 0;
 507 }
 508
 509 void show_boot_progress(int val)
 510 {
 511         if (val < -32) val = -1;  /* let things compatible */
 512         outb(val&0xff, 0x80);
 513         outb((val&0xff00)>>8, 0x680);
 514 }
 515
 516
 517 int last_stage_init(void)
 518 {
 519         int minor;
 520         int major;
 521
 522         major = minor = 0;
 523         major |= ali512x_cio_in(23)?2:0;
 524         major |= ali512x_cio_in(22)?1:0;
 525         minor |= ali512x_cio_in(21)?2:0;
 526         minor |= ali512x_cio_in(20)?1:0;
 527
 528         printf("AMD SC520 CDP revision %d.%d\n", major, minor);
 529
 530         return 0;
 531 }
 532
 533
 534 void ssi_chip_select(int dev)
 535 {
 536
 537         /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
 538         switch (dev) {
 539         case 1: /* SPI EEPROM */
 540                 ali512x_cio_out(16, 0);
 541                 break;
 542
 543         case 2: /* MW EEPROM */
 544                 ali512x_cio_out(15, 1);
 545                 break;
 546
 547         case 3: /* AUX */
 548                 ali512x_cio_out(14, 1);
 549                 break;
 550
 551         case 0:
 552                 ali512x_cio_out(16, 1);
 553                 ali512x_cio_out(15, 0);
 554                 ali512x_cio_out(14, 0);
 555                 break;
 556
 557         default:
 558                 printf("Illegal SSI device requested: %d\n", dev);
 559         }
 560 }
 561
 562 void spi_eeprom_probe(int x)
 563 {
 564 }
 565
 566 int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
 567 {
 568        return 0;
 569 }
 570
 571 int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
 572 {
 573        return 0;
 574 }
 575
 576 void spi_init_f(void)
 577 {
 578 #ifdef CONFIG_SC520_CDP_USE_SPI
 579         spi_eeprom_probe(1);
 580 #endif
 581 #ifdef CONFIG_SC520_CDP_USE_MW
 582         mw_eeprom_probe(2);
 583 #endif
 584 }
 585
 586 ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 587 {
 588         int offset;
 589         int i;
 590         ssize_t res;
 591
 592         offset = 0;
 593         for (i=0;i<alen;i++) {
 594                 offset <<= 8;
 595                 offset |= addr[i];
 596         }
 597
 598 #ifdef CONFIG_SC520_CDP_USE_SPI
 599         res = spi_eeprom_read(1, offset, buffer, len);
 600 #endif
 601 #ifdef CONFIG_SC520_CDP_USE_MW
 602         res = mw_eeprom_read(2, offset, buffer, len);
 603 #endif
 604 #if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
 605         res = 0;
 606 #endif
 607         return res;
 608 }
 609
 610 ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 611 {
 612         int offset;
 613         int i;
 614         ssize_t res;
 615
 616         offset = 0;
 617         for (i=0;i<alen;i++) {
 618                 offset <<= 8;
 619                 offset |= addr[i];
 620         }
 621
 622 #ifdef CONFIG_SC520_CDP_USE_SPI
 623         res = spi_eeprom_write(1, offset, buffer, len);
 624 #endif
 625 #ifdef CONFIG_SC520_CDP_USE_MW
 626         res = mw_eeprom_write(2, offset, buffer, len);
 627 #endif
 628 #if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
 629         res = 0;
 630 #endif
 631         return res;
 632 }
 633
 634 int board_eth_init(bd_t *bis)
 635 {
 636         return pci_eth_init(bis);
 637 }