board/sc520_spunk/sc520_spunk.c

   1 /*
   2  *
   3  * (C) Copyright 2002
   4  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <ssi.h>
  28 #include <netdev.h>
  29 #include <asm/io.h>
  30 #include <asm/pci.h>
  31 #include <asm/ic/sc520.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /*
  36  * Theory:
  37  * We first set up all IRQs to be non-pci, edge triggered,
  38  * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
  39  * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
  40  * as needed. Whe choose the irqs to gram from a configurable list
  41  * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
  42  * such as 0 thngas will not work)
  43  */
  44
  45 static void irq_init(void)
  46 {
  47         /* disable global interrupt mode */
  48         write_mmcr_byte(SC520_PICICR, 0x40);
  49
  50         /* set all irqs to edge */
  51         write_mmcr_byte(SC520_MPICMODE, 0x00);
  52         write_mmcr_byte(SC520_SL1PICMODE, 0x00);
  53         write_mmcr_byte(SC520_SL2PICMODE, 0x00);
  54
  55         /* active low polarity on PIC interrupt pins,
  56          *  active high polarity on all other irq pins */
  57         write_mmcr_word(SC520_INTPINPOL, 0x0000);
  58
  59         /* set irq number mapping */
  60         write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
  61         write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
  62         write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
  63         write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
  64         write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
  65         write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
  66         write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
  67         write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
  68         write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
  69         write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
  70         write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
  71         write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
  72         write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
  73         write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
  74         write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
  75         write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
  76         write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
  77
  78         write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
  79         write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
  80
  81         write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
  82         write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
  83         write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
  84         write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
  85         write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
  86         write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
  87         write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
  88         write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
  89         write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
  90         write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
  91         write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */
  92
  93         write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
  94         write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
  95
  96 }
  97
  98
  99 /* PCI stuff */
 100 static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 101 {
 102         int version = read_mmcr_byte(SC520_SYSINFO);
 103
 104         /* a configurable lists of irqs to steal
 105          * when we need one (a board with more pci interrupt pins
 106          * would use a larger table */
 107         static int irq_list[] = {
 108                 CONFIG_SYS_FIRST_PCI_IRQ,
 109                 CONFIG_SYS_SECOND_PCI_IRQ,
 110                 CONFIG_SYS_THIRD_PCI_IRQ,
 111                 CONFIG_SYS_FORTH_PCI_IRQ
 112         };
 113         static int next_irq_index=0;
 114
 115         char tmp_pin;
 116         int pin;
 117
 118         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
 119         pin = tmp_pin;
 120
 121         pin-=1; /* pci config space use 1-based numbering */
 122         if (-1 == pin) {
 123                 return; /* device use no irq */
 124         }
 125
 126
 127         /* map device number +  pin to a pin on the sc520 */
 128         switch (PCI_DEV(dev)) {
 129         case 6:  /* ETH0 */
 130                 pin+=SC520_PCI_INTA;
 131                 break;
 132
 133         case 7:  /* ETH1 */
 134                 pin+=SC520_PCI_INTB;
 135                 break;
 136
 137         case 8:  /* Crypto */
 138                 pin+=SC520_PCI_INTC;
 139                 break;
 140
 141         case 9: /* PMC slot */
 142                 pin+=SC520_PCI_INTD;
 143                 break;
 144
 145         case 10: /* PC-Card */
 146
 147                 if (version < 10) {
 148                         pin+=SC520_PCI_INTD;
 149                 } else {
 150                         pin+=SC520_PCI_INTC;
 151                 }
 152                 break;
 153
 154         default:
 155                 return;
 156         }
 157
 158         pin&=3; /* wrap around */
 159
 160         if (sc520_pci_ints[pin] == -1) {
 161                 /* re-route one interrupt for us */
 162                 if (next_irq_index > 3) {
 163                         return;
 164                 }
 165                 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
 166                         return;
 167                 }
 168                 next_irq_index++;
 169         }
 170
 171
 172         if (-1 != sc520_pci_ints[pin]) {
 173                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 174                                            sc520_pci_ints[pin]);
 175         }
 176 #if 0
 177         printf("fixup_irq: device %d pin %c irq %d\n",
 178                PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
 179 #endif
 180 }
 181
 182
 183 static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
 184                                               pci_dev_t dev, struct pci_config_table *te)
 185 {
 186         u32 io_base;
 187         u32 temp;
 188
 189         pciauto_config_device(hose, dev);
 190
 191         pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
 192         pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
 193         pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
 194         pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
 195         pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
 196         pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
 197         pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
 198
 199         pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */
 200         pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */
 201         /* route MF0 to ~INT and MF3 to IRQ7
 202          * reserve all others */
 203         pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
 204         pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
 205         pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
 206
 207         if (te->device != 0xac56) {
 208                 pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
 209                 pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
 210                 pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
 211                 pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
 212                 pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
 213         } else {
 214                 pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
 215         }
 216         pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
 217
 218
 219         pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
 220         io_base &= ~0xfL;
 221
 222         writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
 223         writel(0, io_base+0x10);     /* CLKRUN default */
 224         writel(0, io_base+0x20);     /* CLKRUN default */
 225
 226 }
 227
 228
 229 static struct pci_config_table pci_sc520_spunk_config_table[] = {
 230         { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
 231         { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
 232         { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
 233 };
 234
 235 static struct pci_controller sc520_spunk_hose = {
 236         fixup_irq: pci_sc520_spunk_fixup_irq,
 237         config_table: pci_sc520_spunk_config_table,
 238         first_busno: 0x00,
 239         last_busno: 0xff,
 240 };
 241
 242 void pci_init_board(void)
 243 {
 244         pci_sc520_init(&sc520_spunk_hose);
 245 }
 246
 247
 248 /* set up the ISA bus timing and system address mappings */
 249 static void bus_init(void)
 250 {
 251         /* versions
 252          * 0   Hyglo versions 0.95 and 0.96 (large baords)
 253          * ??  Hyglo version 0.97 (small board)
 254          * 10  Spunk board
 255          */
 256         int version = read_mmcr_byte(SC520_SYSINFO);
 257
 258         if (version) {
 259                 /* set up the GP IO pins (for the Spunk board) */
 260                 write_mmcr_word(SC520_PIOPFS31_16, 0xfff0);     /* set the GPIO pin function 31-16 reg */
 261                 write_mmcr_word(SC520_PIOPFS15_0,  0x000f);     /* set the GPIO pin function 15-0 reg */
 262                 write_mmcr_word(SC520_PIODIR31_16, 0x000f);     /* set the GPIO direction 31-16 reg */
 263                 write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);     /* set the GPIO direction 15-0 reg */
 264                 write_mmcr_byte(SC520_CSPFS, 0xc0);             /* set the CS pin function reg */
 265                 write_mmcr_byte(SC520_CLKSEL, 0x70);
 266
 267                 write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
 268                 write_mmcr_word(SC520_PIOSET31_16, 0x000c);
 269
 270         } else {
 271                 /* set up the GP IO pins (for the Hyglo board) */
 272                 write_mmcr_word(SC520_PIOPFS31_16, 0xffc0);     /* set the GPIO pin function 31-16 reg */
 273                 write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);      /* set the GPIO pin function 15-0 reg */
 274                 write_mmcr_word(SC520_PIODIR31_16, 0x003f);     /* set the GPIO direction 31-16 reg */
 275                 write_mmcr_word(SC520_PIODIR15_0, 0xe180);      /* set the GPIO direction 15-0 reg */
 276                 write_mmcr_byte(SC520_CSPFS, 0x00);             /* set the CS pin function reg */
 277                 write_mmcr_byte(SC520_CLKSEL, 0x70);
 278
 279                 write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
 280         }
 281
 282         write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
 283         write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
 284         write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
 285         write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
 286         write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
 287         write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
 288         write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
 289
 290         write_mmcr_word(SC520_BOOTCSCTL, 0x0407);               /* set up timing of BOOTCS */
 291
 292         /* adjust the memory map:
 293          * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
 294          * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
 295          * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
 296
 297
 298         /* bootcs */
 299         write_mmcr_long(SC520_PAR12, 0x8bffe800);
 300
 301         /* IDE0 = GPCS6 1f0-1f7 */
 302         write_mmcr_long(SC520_PAR3,  0x380801f0);
 303
 304         /* IDE1 = GPCS7 3f6 */
 305         write_mmcr_long(SC520_PAR4,  0x3c0003f6);
 306
 307         asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 308
 309         write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
 310
 311 }
 312
 313
 314 /* par usage:
 315  * PAR0   (legacy_video)
 316  * PAR1   (PCI ROM mapping)
 317  * PAR2
 318  * PAR3   IDE
 319  * PAR4   IDE
 320  * PAR5   (legacy_video)
 321  * PAR6
 322  * PAR7   (legacy_video)
 323  * PAR8   (legacy_video)
 324  * PAR9   (legacy_video)
 325  * PAR10
 326  * PAR11  (ISAROM)
 327  * PAR12  BOOTCS
 328  * PAR13
 329  * PAR14
 330  * PAR15
 331  */
 332
 333 /*
 334  * This function should map a chunk of size bytes
 335  * of the system address space to the ISA bus
 336  *
 337  * The function will return the memory address
 338  * as seen by the host (which may very will be the
 339  * same as the bus address)
 340  */
 341 u32 isa_map_rom(u32 bus_addr, int size)
 342 {
 343         u32 par;
 344
 345         printf("isa_map_rom asked to map %d bytes at %x\n",
 346                size, bus_addr);
 347
 348         par = size;
 349         if (par < 0x80000) {
 350                 par = 0x80000;
 351         }
 352         par >>= 12;
 353         par--;
 354         par&=0x7f;
 355         par <<= 18;
 356         par |= (bus_addr>>12);
 357         par |= 0x50000000;
 358
 359         printf ("setting PAR11 to %x\n", par);
 360
 361         /* Map rom 0x10000 with PAR1 */
 362         write_mmcr_long(SC520_PAR11,  par);
 363
 364         return bus_addr;
 365 }
 366
 367 /*
 368  * this function removed any mapping created
 369  * with pci_get_rom_window()
 370  */
 371 void isa_unmap_rom(u32 addr)
 372 {
 373         printf("isa_unmap_rom asked to unmap %x", addr);
 374         if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
 375                 write_mmcr_long(SC520_PAR11, 0);
 376                 printf(" done\n");
 377                 return;
 378         }
 379         printf(" not ours\n");
 380 }
 381
 382 #ifdef CONFIG_PCI
 383 #define PCI_ROM_TEMP_SPACE 0x10000
 384 /*
 385  * This function should map a chunk of size bytes
 386  * of the system address space to the PCI bus,
 387  * suitable to map PCI ROMS (bus address < 16M)
 388  * the function will return the host memory address
 389  * which should be converted into a bus address
 390  * before used to configure the PCI rom address
 391  * decoder
 392  */
 393 u32 pci_get_rom_window(struct pci_controller *hose, int size)
 394 {
 395         u32 par;
 396
 397         par = size;
 398         if (par < 0x80000) {
 399                 par = 0x80000;
 400         }
 401         par >>= 16;
 402         par--;
 403         par&=0x7ff;
 404         par <<= 14;
 405         par |= (PCI_ROM_TEMP_SPACE>>16);
 406         par |= 0x72000000;
 407
 408         printf ("setting PAR1 to %x\n", par);
 409
 410         /* Map rom 0x10000 with PAR1 */
 411         write_mmcr_long(SC520_PAR1,  par);
 412
 413         return PCI_ROM_TEMP_SPACE;
 414 }
 415
 416 /*
 417  * this function removed any mapping created
 418  * with pci_get_rom_window()
 419  */
 420 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 421 {
 422         printf("pci_remove_rom_window: %x", addr);
 423         if (addr == PCI_ROM_TEMP_SPACE) {
 424                 write_mmcr_long(SC520_PAR1, 0);
 425                 printf(" done\n");
 426                 return;
 427         }
 428         printf(" not ours\n");
 429
 430 }
 431
 432 /*
 433  * This function is called in order to provide acces to the
 434  * legacy video I/O ports on the PCI bus.
 435  * After this function accesses to I/O ports 0x3b0-0x3bb and
 436  * 0x3c0-0x3df shuld result in transactions on the PCI bus.
 437  *
 438  */
 439 int pci_enable_legacy_video_ports(struct pci_controller *hose)
 440 {
 441         /* Map video memory to 0xa0000*/
 442         write_mmcr_long(SC520_PAR0,  0x7200400a);
 443
 444         /* forward all I/O accesses to PCI */
 445         write_mmcr_byte(SC520_ADDDECCTL,
 446                         read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
 447
 448
 449         /* so we map away all io ports to pci (only way to access pci io
 450          * below 0x400. But then we have to map back the portions that we dont
 451          * use so that the generate cycles on the GPIO bus where the sio and
 452          * ISA slots are connected, this requre the use of several PAR registers
 453          */
 454
 455         /* bring 0x100 - 0x2f7 back to ISA using PAR5 */
 456         write_mmcr_long(SC520_PAR5, 0x31f70100);
 457
 458         /* com2 use 2f8-2ff */
 459
 460         /* bring 0x300 - 0x3af back to ISA using PAR7 */
 461         write_mmcr_long(SC520_PAR7, 0x30af0300);
 462
 463         /* vga use 3b0-3bb */
 464
 465         /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
 466         write_mmcr_long(SC520_PAR8, 0x300303bc);
 467
 468         /* vga use 3c0-3df */
 469
 470         /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
 471         write_mmcr_long(SC520_PAR9, 0x301703e0);
 472
 473         /* com1 use 3f8-3ff */
 474
 475         return 0;
 476 }
 477 #endif
 478
 479 /*
 480  * Miscelaneous platform dependent initialisations
 481  */
 482
 483 int board_init(void)
 484 {
 485         init_sc520();
 486         bus_init();
 487         irq_init();
 488
 489         /* max drive current on SDRAM */
 490         write_mmcr_word(SC520_DSCTL, 0x0100);
 491
 492         /* enter debug mode after next reset (only if jumper is also set) */
 493         write_mmcr_byte(SC520_RESCFG, 0x08);
 494         /* configure the software timer to 33.000MHz */
 495         write_mmcr_byte(SC520_SWTMRCFG, 1);
 496         gd->bus_clk = 33000000;
 497
 498         return 0;
 499 }
 500
 501 int dram_init(void)
 502 {
 503         init_sc520_dram();
 504         return 0;
 505 }
 506
 507 void show_boot_progress(int val)
 508 {
 509         int version = read_mmcr_byte(SC520_SYSINFO);
 510
 511         if (val < -32) val = -1;  /* let things compatible */
 512         if (version == 0) {
 513                 /* PIO31-PIO16 Data */
 514                 write_mmcr_word(SC520_PIODATA31_16,
 515                                 (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
 516
 517                 /* PIO0-PIO15 Data */
 518                 write_mmcr_word(SC520_PIODATA15_0,
 519                                 (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
 520         } else {
 521                 /* newer boards use PIO4-PIO12 */
 522                 /* PIO0-PIO15 Data */
 523 #if 0
 524                 val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3);
 525 #else
 526                 val = (val & 0x007) | ((val & 0x07e) << 2);
 527 #endif
 528                 write_mmcr_word(SC520_PIODATA15_0,
 529                                 (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
 530         }
 531 }
 532
 533
 534 int last_stage_init(void)
 535 {
 536
 537         int version = read_mmcr_byte(SC520_SYSINFO);
 538
 539         printf("Omicron Ceti SC520 Spunk revision %x\n", version);
 540
 541 #if 0
 542         if (version) {
 543                 int x, y;
 544
 545                 printf("eeprom probe %d\n", spi_eeprom_probe(1));
 546
 547                 spi_eeprom_read(1, 0, (u8*)&x, 2);
 548                 spi_eeprom_read(1, 1, (u8*)&y, 2);
 549                 printf("eeprom bytes %04x%04x\n", x, y);
 550                 x ^= 0xffff;
 551                 y ^= 0xffff;
 552                 spi_eeprom_write(1, 0, (u8*)&x, 2);
 553                 spi_eeprom_write(1, 1, (u8*)&y, 2);
 554
 555                 spi_eeprom_read(1, 0, (u8*)&x, 2);
 556                 spi_eeprom_read(1, 1, (u8*)&y, 2);
 557                 printf("eeprom bytes %04x%04x\n", x, y);
 558
 559         } else {
 560                 int x, y;
 561
 562                 printf("eeprom probe %d\n", mw_eeprom_probe(1));
 563
 564                 mw_eeprom_read(1, 0, (u8*)&x, 2);
 565                 mw_eeprom_read(1, 1, (u8*)&y, 2);
 566                 printf("eeprom bytes %04x%04x\n", x, y);
 567
 568                 x ^= 0xffff;
 569                 y ^= 0xffff;
 570                 mw_eeprom_write(1, 0, (u8*)&x, 2);
 571                 mw_eeprom_write(1, 1, (u8*)&y, 2);
 572
 573                 mw_eeprom_read(1, 0, (u8*)&x, 2);
 574                 mw_eeprom_read(1, 1, (u8*)&y, 2);
 575                 printf("eeprom bytes %04x%04x\n", x, y);
 576
 577
 578         }
 579 #endif
 580
 581         ds1722_probe(2);
 582
 583         return 0;
 584 }
 585
 586 void ssi_chip_select(int dev)
 587 {
 588         int version = read_mmcr_byte(SC520_SYSINFO);
 589
 590         if (version) {
 591                 /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
 592                 switch (dev) {
 593                 case 1: /* EEPROM */
 594                         write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
 595                         break;
 596
 597                 case 2: /* Temp Probe */
 598                         write_mmcr_word(SC520_PIOSET31_16, 0x0002);
 599                         break;
 600
 601                 case 3: /* CAN */
 602                         write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
 603                         break;
 604
 605                 case 4: /* AUX */
 606                         write_mmcr_word(SC520_PIOSET31_16, 0x0001);
 607                         break;
 608
 609                 case 0:
 610                         write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
 611                         write_mmcr_word(SC520_PIOSET31_16, 0x000c);
 612                         break;
 613
 614                 default:
 615                         printf("Illegal SSI device requested: %d\n", dev);
 616                 }
 617         } else {
 618
 619                 /* Globox board: Both EEPROM and TEMP are active-high */
 620
 621                 switch (dev) {
 622                 case 1: /* EEPROM */
 623                         write_mmcr_word(SC520_PIOSET15_0, 0x0100);
 624                         break;
 625
 626                 case 2: /* Temp Probe */
 627                         write_mmcr_word(SC520_PIOSET15_0, 0x0080);
 628                         break;
 629
 630                 case 0:
 631                         write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
 632                         break;
 633
 634                 default:
 635                         printf("Illegal SSI device requested: %d\n", dev);
 636                 }
 637         }
 638 }
 639
 640
 641 void spi_init_f(void)
 642 {
 643         read_mmcr_byte(SC520_SYSINFO) ?
 644                 spi_eeprom_probe(1) :
 645         mw_eeprom_probe(1);
 646
 647 }
 648
 649 ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 650 {
 651         int offset;
 652         int i;
 653
 654         offset = 0;
 655         for (i=0;i<alen;i++) {
 656                 offset <<= 8;
 657                 offset |= addr[i];
 658         }
 659
 660         return  read_mmcr_byte(SC520_SYSINFO) ?
 661                 spi_eeprom_read(1, offset, buffer, len) :
 662         mw_eeprom_read(1, offset, buffer, len);
 663 }
 664
 665 ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 666 {
 667         int offset;
 668         int i;
 669
 670         offset = 0;
 671         for (i=0;i<alen;i++) {
 672                 offset <<= 8;
 673                 offset |= addr[i];
 674         }
 675
 676         return  read_mmcr_byte(SC520_SYSINFO) ?
 677                 spi_eeprom_write(1, offset, buffer, len) :
 678         mw_eeprom_write(1, offset, buffer, len);
 679 }
 680
 681 int board_eth_init(bd_t *bis)
 682 {
 683         return pci_eth_init(bis);
 684 }