board/sc520_spunk/sc520_spunk.c

   1 /*
   2  *
   3  * (C) Copyright 2002
   4  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <ssi.h>
  28 #include <asm/io.h>
  29 #include <asm/pci.h>
  30 #include <asm/ic/sc520.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /*
  35  * Theory:
  36  * We first set up all IRQs to be non-pci, edge triggered,
  37  * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
  38  * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
  39  * as needed. Whe choose the irqs to gram from a configurable list
  40  * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
  41  * such as 0 thngas will not work)
  42  */
  43
  44 static void irq_init(void)
  45 {
  46         /* disable global interrupt mode */
  47         write_mmcr_byte(SC520_PICICR, 0x40);
  48
  49         /* set all irqs to edge */
  50         write_mmcr_byte(SC520_MPICMODE, 0x00);
  51         write_mmcr_byte(SC520_SL1PICMODE, 0x00);
  52         write_mmcr_byte(SC520_SL2PICMODE, 0x00);
  53
  54         /* active low polarity on PIC interrupt pins,
  55          *  active high polarity on all other irq pins */
  56         write_mmcr_word(SC520_INTPINPOL, 0x0000);
  57
  58         /* set irq number mapping */
  59         write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
  60         write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
  61         write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
  62         write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
  63         write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
  64         write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
  65         write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
  66         write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
  67         write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
  68         write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
  69         write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
  70         write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
  71         write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
  72         write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
  73         write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
  74         write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
  75         write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
  76
  77         write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
  78         write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
  79
  80         write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
  81         write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
  82         write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
  83         write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
  84         write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
  85         write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
  86         write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
  87         write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
  88         write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
  89         write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
  90         write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */
  91
  92         write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
  93         write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
  94
  95 }
  96
  97
  98 /* PCI stuff */
  99 static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 100 {
 101         int version = read_mmcr_byte(SC520_SYSINFO);
 102
 103         /* a configurable lists of irqs to steal
 104          * when we need one (a board with more pci interrupt pins
 105          * would use a larger table */
 106         static int irq_list[] = {
 107                 CFG_FIRST_PCI_IRQ,
 108                 CFG_SECOND_PCI_IRQ,
 109                 CFG_THIRD_PCI_IRQ,
 110                 CFG_FORTH_PCI_IRQ
 111         };
 112         static int next_irq_index=0;
 113
 114         char tmp_pin;
 115         int pin;
 116
 117         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
 118         pin = tmp_pin;
 119
 120         pin-=1; /* pci config space use 1-based numbering */
 121         if (-1 == pin) {
 122                 return; /* device use no irq */
 123         }
 124
 125
 126         /* map device number +  pin to a pin on the sc520 */
 127         switch (PCI_DEV(dev)) {
 128         case 6:  /* ETH0 */
 129                 pin+=SC520_PCI_INTA;
 130                 break;
 131
 132         case 7:  /* ETH1 */
 133                 pin+=SC520_PCI_INTB;
 134                 break;
 135
 136         case 8:  /* Crypto */
 137                 pin+=SC520_PCI_INTC;
 138                 break;
 139
 140         case 9: /* PMC slot */
 141                 pin+=SC520_PCI_INTD;
 142                 break;
 143
 144         case 10: /* PC-Card */
 145
 146                 if (version < 10) {
 147                         pin+=SC520_PCI_INTD;
 148                 } else {
 149                         pin+=SC520_PCI_INTC;
 150                 }
 151                 break;
 152
 153         default:
 154                 return;
 155         }
 156
 157         pin&=3; /* wrap around */
 158
 159         if (sc520_pci_ints[pin] == -1) {
 160                 /* re-route one interrupt for us */
 161                 if (next_irq_index > 3) {
 162                         return;
 163                 }
 164                 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
 165                         return;
 166                 }
 167                 next_irq_index++;
 168         }
 169
 170
 171         if (-1 != sc520_pci_ints[pin]) {
 172                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 173                                            sc520_pci_ints[pin]);
 174         }
 175 #if 0
 176         printf("fixup_irq: device %d pin %c irq %d\n",
 177                PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
 178 #endif
 179 }
 180
 181
 182 static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
 183                                               pci_dev_t dev, struct pci_config_table *te)
 184 {
 185         u32 io_base;
 186         u32 temp;
 187
 188         pciauto_config_device(hose, dev);
 189
 190         pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
 191         pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
 192         pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
 193         pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
 194         pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
 195         pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
 196         pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
 197
 198         pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */
 199         pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */
 200         /* route MF0 to ~INT and MF3 to IRQ7
 201          * reserve all others */
 202         pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
 203         pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
 204         pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
 205
 206         if (te->device != 0xac56) {
 207                 pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
 208                 pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
 209                 pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
 210                 pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
 211                 pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
 212         } else {
 213                 pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
 214         }
 215         pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
 216
 217
 218         pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
 219         io_base &= ~0xfL;
 220
 221         writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
 222         writel(0, io_base+0x10);     /* CLKRUN default */
 223         writel(0, io_base+0x20);     /* CLKRUN default */
 224
 225 }
 226
 227
 228 static struct pci_config_table pci_sc520_spunk_config_table[] = {
 229         { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
 230         { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
 231         { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
 232 };
 233
 234 static struct pci_controller sc520_spunk_hose = {
 235         fixup_irq: pci_sc520_spunk_fixup_irq,
 236         config_table: pci_sc520_spunk_config_table,
 237         first_busno: 0x00,
 238         last_busno: 0xff,
 239 };
 240
 241 void pci_init_board(void)
 242 {
 243         pci_sc520_init(&sc520_spunk_hose);
 244 }
 245
 246
 247 /* set up the ISA bus timing and system address mappings */
 248 static void bus_init(void)
 249 {
 250         /* versions
 251          * 0   Hyglo versions 0.95 and 0.96 (large baords)
 252          * ??  Hyglo version 0.97 (small board)
 253          * 10  Spunk board
 254          */
 255         int version = read_mmcr_byte(SC520_SYSINFO);
 256
 257         if (version) {
 258                 /* set up the GP IO pins (for the Spunk board) */
 259                 write_mmcr_word(SC520_PIOPFS31_16, 0xfff0);     /* set the GPIO pin function 31-16 reg */
 260                 write_mmcr_word(SC520_PIOPFS15_0,  0x000f);     /* set the GPIO pin function 15-0 reg */
 261                 write_mmcr_word(SC520_PIODIR31_16, 0x000f);     /* set the GPIO direction 31-16 reg */
 262                 write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);     /* set the GPIO direction 15-0 reg */
 263                 write_mmcr_byte(SC520_CSPFS, 0xc0);             /* set the CS pin function reg */
 264                 write_mmcr_byte(SC520_CLKSEL, 0x70);
 265
 266                 write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
 267                 write_mmcr_word(SC520_PIOSET31_16, 0x000c);
 268
 269         } else {
 270                 /* set up the GP IO pins (for the Hyglo board) */
 271                 write_mmcr_word(SC520_PIOPFS31_16, 0xffc0);     /* set the GPIO pin function 31-16 reg */
 272                 write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);      /* set the GPIO pin function 15-0 reg */
 273                 write_mmcr_word(SC520_PIODIR31_16, 0x003f);     /* set the GPIO direction 31-16 reg */
 274                 write_mmcr_word(SC520_PIODIR15_0, 0xe180);      /* set the GPIO direction 15-0 reg */
 275                 write_mmcr_byte(SC520_CSPFS, 0x00);             /* set the CS pin function reg */
 276                 write_mmcr_byte(SC520_CLKSEL, 0x70);
 277
 278                 write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
 279         }
 280
 281         write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
 282         write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
 283         write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
 284         write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
 285         write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
 286         write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
 287         write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
 288
 289         write_mmcr_word(SC520_BOOTCSCTL, 0x0407);               /* set up timing of BOOTCS */
 290
 291         /* adjust the memory map:
 292          * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
 293          * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
 294          * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
 295
 296
 297         /* bootcs */
 298         write_mmcr_long(SC520_PAR12, 0x8bffe800);
 299
 300         /* IDE0 = GPCS6 1f0-1f7 */
 301         write_mmcr_long(SC520_PAR3,  0x380801f0);
 302
 303         /* IDE1 = GPCS7 3f6 */
 304         write_mmcr_long(SC520_PAR4,  0x3c0003f6);
 305
 306         asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 307
 308         write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
 309
 310 }
 311
 312
 313 /* par usage:
 314  * PAR0   (legacy_video)
 315  * PAR1   (PCI ROM mapping)
 316  * PAR2
 317  * PAR3   IDE
 318  * PAR4   IDE
 319  * PAR5   (legacy_video)
 320  * PAR6
 321  * PAR7   (legacy_video)
 322  * PAR8   (legacy_video)
 323  * PAR9   (legacy_video)
 324  * PAR10
 325  * PAR11  (ISAROM)
 326  * PAR12  BOOTCS
 327  * PAR13
 328  * PAR14
 329  * PAR15
 330  */
 331
 332 /*
 333  * This function should map a chunk of size bytes
 334  * of the system address space to the ISA bus
 335  *
 336  * The function will return the memory address
 337  * as seen by the host (which may very will be the
 338  * same as the bus address)
 339  */
 340 u32 isa_map_rom(u32 bus_addr, int size)
 341 {
 342         u32 par;
 343
 344         printf("isa_map_rom asked to map %d bytes at %x\n",
 345                size, bus_addr);
 346
 347         par = size;
 348         if (par < 0x80000) {
 349                 par = 0x80000;
 350         }
 351         par >>= 12;
 352         par--;
 353         par&=0x7f;
 354         par <<= 18;
 355         par |= (bus_addr>>12);
 356         par |= 0x50000000;
 357
 358         printf ("setting PAR11 to %x\n", par);
 359
 360         /* Map rom 0x10000 with PAR1 */
 361         write_mmcr_long(SC520_PAR11,  par);
 362
 363         return bus_addr;
 364 }
 365
 366 /*
 367  * this function removed any mapping created
 368  * with pci_get_rom_window()
 369  */
 370 void isa_unmap_rom(u32 addr)
 371 {
 372         printf("isa_unmap_rom asked to unmap %x", addr);
 373         if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
 374                 write_mmcr_long(SC520_PAR11, 0);
 375                 printf(" done\n");
 376                 return;
 377         }
 378         printf(" not ours\n");
 379 }
 380
 381 #ifdef CONFIG_PCI
 382 #define PCI_ROM_TEMP_SPACE 0x10000
 383 /*
 384  * This function should map a chunk of size bytes
 385  * of the system address space to the PCI bus,
 386  * suitable to map PCI ROMS (bus address < 16M)
 387  * the function will return the host memory address
 388  * which should be converted into a bus address
 389  * before used to configure the PCI rom address
 390  * decoder
 391  */
 392 u32 pci_get_rom_window(struct pci_controller *hose, int size)
 393 {
 394         u32 par;
 395
 396         par = size;
 397         if (par < 0x80000) {
 398                 par = 0x80000;
 399         }
 400         par >>= 16;
 401         par--;
 402         par&=0x7ff;
 403         par <<= 14;
 404         par |= (PCI_ROM_TEMP_SPACE>>16);
 405         par |= 0x72000000;
 406
 407         printf ("setting PAR1 to %x\n", par);
 408
 409         /* Map rom 0x10000 with PAR1 */
 410         write_mmcr_long(SC520_PAR1,  par);
 411
 412         return PCI_ROM_TEMP_SPACE;
 413 }
 414
 415 /*
 416  * this function removed any mapping created
 417  * with pci_get_rom_window()
 418  */
 419 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 420 {
 421         printf("pci_remove_rom_window: %x", addr);
 422         if (addr == PCI_ROM_TEMP_SPACE) {
 423                 write_mmcr_long(SC520_PAR1, 0);
 424                 printf(" done\n");
 425                 return;
 426         }
 427         printf(" not ours\n");
 428
 429 }
 430
 431 /*
 432  * This function is called in order to provide acces to the
 433  * legacy video I/O ports on the PCI bus.
 434  * After this function accesses to I/O ports 0x3b0-0x3bb and
 435  * 0x3c0-0x3df shuld result in transactions on the PCI bus.
 436  *
 437  */
 438 int pci_enable_legacy_video_ports(struct pci_controller *hose)
 439 {
 440         /* Map video memory to 0xa0000*/
 441         write_mmcr_long(SC520_PAR0,  0x7200400a);
 442
 443         /* forward all I/O accesses to PCI */
 444         write_mmcr_byte(SC520_ADDDECCTL,
 445                         read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
 446
 447
 448         /* so we map away all io ports to pci (only way to access pci io
 449          * below 0x400. But then we have to map back the portions that we dont
 450          * use so that the generate cycles on the GPIO bus where the sio and
 451          * ISA slots are connected, this requre the use of several PAR registers
 452          */
 453
 454         /* bring 0x100 - 0x2f7 back to ISA using PAR5 */
 455         write_mmcr_long(SC520_PAR5, 0x31f70100);
 456
 457         /* com2 use 2f8-2ff */
 458
 459         /* bring 0x300 - 0x3af back to ISA using PAR7 */
 460         write_mmcr_long(SC520_PAR7, 0x30af0300);
 461
 462         /* vga use 3b0-3bb */
 463
 464         /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
 465         write_mmcr_long(SC520_PAR8, 0x300303bc);
 466
 467         /* vga use 3c0-3df */
 468
 469         /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
 470         write_mmcr_long(SC520_PAR9, 0x301703e0);
 471
 472         /* com1 use 3f8-3ff */
 473
 474         return 0;
 475 }
 476 #endif
 477
 478 /*
 479  * Miscelaneous platform dependent initialisations
 480  */
 481
 482 int board_init(void)
 483 {
 484         init_sc520();
 485         bus_init();
 486         irq_init();
 487
 488         /* max drive current on SDRAM */
 489         write_mmcr_word(SC520_DSCTL, 0x0100);
 490
 491         /* enter debug mode after next reset (only if jumper is also set) */
 492         write_mmcr_byte(SC520_RESCFG, 0x08);
 493         /* configure the software timer to 33.000MHz */
 494         write_mmcr_byte(SC520_SWTMRCFG, 1);
 495         gd->bus_clk = 33000000;
 496
 497         return 0;
 498 }
 499
 500 int dram_init(void)
 501 {
 502         init_sc520_dram();
 503         return 0;
 504 }
 505
 506 void show_boot_progress(int val)
 507 {
 508         int version = read_mmcr_byte(SC520_SYSINFO);
 509
 510         if (val < -32) val = -1;  /* let things compatible */
 511         if (version == 0) {
 512                 /* PIO31-PIO16 Data */
 513                 write_mmcr_word(SC520_PIODATA31_16,
 514                                 (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
 515
 516                 /* PIO0-PIO15 Data */
 517                 write_mmcr_word(SC520_PIODATA15_0,
 518                                 (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
 519         } else {
 520                 /* newer boards use PIO4-PIO12 */
 521                 /* PIO0-PIO15 Data */
 522 #if 0
 523                 val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3);
 524 #else
 525                 val = (val & 0x007) | ((val & 0x07e) << 2);
 526 #endif
 527                 write_mmcr_word(SC520_PIODATA15_0,
 528                                 (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
 529         }
 530 }
 531
 532
 533 int last_stage_init(void)
 534 {
 535
 536         int version = read_mmcr_byte(SC520_SYSINFO);
 537
 538         printf("Omicron Ceti SC520 Spunk revision %x\n", version);
 539
 540 #if 0
 541         if (version) {
 542                 int x, y;
 543
 544                 printf("eeprom probe %d\n", spi_eeprom_probe(1));
 545
 546                 spi_eeprom_read(1, 0, (u8*)&x, 2);
 547                 spi_eeprom_read(1, 1, (u8*)&y, 2);
 548                 printf("eeprom bytes %04x%04x\n", x, y);
 549                 x ^= 0xffff;
 550                 y ^= 0xffff;
 551                 spi_eeprom_write(1, 0, (u8*)&x, 2);
 552                 spi_eeprom_write(1, 1, (u8*)&y, 2);
 553
 554                 spi_eeprom_read(1, 0, (u8*)&x, 2);
 555                 spi_eeprom_read(1, 1, (u8*)&y, 2);
 556                 printf("eeprom bytes %04x%04x\n", x, y);
 557
 558         } else {
 559                 int x, y;
 560
 561                 printf("eeprom probe %d\n", mw_eeprom_probe(1));
 562
 563                 mw_eeprom_read(1, 0, (u8*)&x, 2);
 564                 mw_eeprom_read(1, 1, (u8*)&y, 2);
 565                 printf("eeprom bytes %04x%04x\n", x, y);
 566
 567                 x ^= 0xffff;
 568                 y ^= 0xffff;
 569                 mw_eeprom_write(1, 0, (u8*)&x, 2);
 570                 mw_eeprom_write(1, 1, (u8*)&y, 2);
 571
 572                 mw_eeprom_read(1, 0, (u8*)&x, 2);
 573                 mw_eeprom_read(1, 1, (u8*)&y, 2);
 574                 printf("eeprom bytes %04x%04x\n", x, y);
 575
 576
 577         }
 578 #endif
 579
 580         ds1722_probe(2);
 581
 582         return 0;
 583 }
 584
 585 void ssi_chip_select(int dev)
 586 {
 587         int version = read_mmcr_byte(SC520_SYSINFO);
 588
 589         if (version) {
 590                 /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
 591                 switch (dev) {
 592                 case 1: /* EEPROM */
 593                         write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
 594                         break;
 595
 596                 case 2: /* Temp Probe */
 597                         write_mmcr_word(SC520_PIOSET31_16, 0x0002);
 598                         break;
 599
 600                 case 3: /* CAN */
 601                         write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
 602                         break;
 603
 604                 case 4: /* AUX */
 605                         write_mmcr_word(SC520_PIOSET31_16, 0x0001);
 606                         break;
 607
 608                 case 0:
 609                         write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
 610                         write_mmcr_word(SC520_PIOSET31_16, 0x000c);
 611                         break;
 612
 613                 default:
 614                         printf("Illegal SSI device requested: %d\n", dev);
 615                 }
 616         } else {
 617
 618                 /* Globox board: Both EEPROM and TEMP are active-high */
 619
 620                 switch (dev) {
 621                 case 1: /* EEPROM */
 622                         write_mmcr_word(SC520_PIOSET15_0, 0x0100);
 623                         break;
 624
 625                 case 2: /* Temp Probe */
 626                         write_mmcr_word(SC520_PIOSET15_0, 0x0080);
 627                         break;
 628
 629                 case 0:
 630                         write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
 631                         break;
 632
 633                 default:
 634                         printf("Illegal SSI device requested: %d\n", dev);
 635                 }
 636         }
 637 }
 638
 639
 640 void spi_init_f(void)
 641 {
 642         read_mmcr_byte(SC520_SYSINFO) ?
 643                 spi_eeprom_probe(1) :
 644         mw_eeprom_probe(1);
 645
 646 }
 647
 648 ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 649 {
 650         int offset;
 651         int i;
 652
 653         offset = 0;
 654         for (i=0;i<alen;i++) {
 655                 offset <<= 8;
 656                 offset |= addr[i];
 657         }
 658
 659         return  read_mmcr_byte(SC520_SYSINFO) ?
 660                 spi_eeprom_read(1, offset, buffer, len) :
 661         mw_eeprom_read(1, offset, buffer, len);
 662 }
 663
 664 ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 665 {
 666         int offset;
 667         int i;
 668
 669         offset = 0;
 670         for (i=0;i<alen;i++) {
 671                 offset <<= 8;
 672                 offset |= addr[i];
 673         }
 674
 675         return  read_mmcr_byte(SC520_SYSINFO) ?
 676                 spi_eeprom_write(1, offset, buffer, len) :
 677         mw_eeprom_write(1, offset, buffer, len);
 678 }