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* Code cleanup:
[u-boot.git] / board / siemens / SCM / scm.c
1 /*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <ioports.h>
26 #include <mpc8260.h>
27
28 #include "scm.h"
29
30 static void config_scoh_cs(void);
31 extern int fpga_init(void);
32
33 #if 0
34 #define DEBUGF(fmt,args...) printf (fmt ,##args)
35 #else
36 #define DEBUGF(fmt,args...)
37 #endif
38
39 /*
40 * I/O Port configuration table
41 *
42 * if conf is 1, then that port pin will be configured at boot time
43 * according to the five values podr/pdir/ppar/psor/pdat for that entry
44 */
45
46 const iop_conf_t iop_conf_tab[4][32] = {
47
48 /* Port A configuration */
49 { /* conf ppar psor pdir podr pdat */
50 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
51 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
52 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
53 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
54 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
55 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
56 /* PA25 */ { 0, 0, 0, 1, 0, 0 },
57 /* PA24 */ { 0, 0, 0, 1, 0, 0 },
58 /* PA23 */ { 0, 0, 0, 1, 0, 0 },
59 /* PA22 */ { 0, 0, 0, 1, 0, 0 },
60 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
61 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
62 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
63 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
64 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
65 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/
66 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
67 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
68 /* PA13 */ { 0, 0, 0, 1, 0, 0 },
69 /* PA12 */ { 0, 0, 0, 1, 0, 0 },
70 /* PA11 */ { 0, 0, 0, 1, 0, 0 },
71 /* PA10 */ { 0, 0, 0, 1, 0, 0 },
72 /* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */
73 /* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */
74 /* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */
75 /* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */
76 /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */
77 /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */
78 /* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */
79 /* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */
80 /* PA1 */ { 0, 0, 0, 1, 0, 0 },
81 /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */
82 },
83
84 /* Port B configuration */
85 { /* conf ppar psor pdir podr pdat */
86 /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */
87 /* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */
88 /* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */
89 /* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */
90 /* PB27 */ { 0, 1, 0, 0, 0, 0 },
91 /* PB26 */ { 0, 1, 0, 0, 0, 0 },
92 /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */
93 /* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */
94 /* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */
95 /* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */
96 /* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */
97 /* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */
98 /* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */
99 /* PB18 */ { 0, 1, 0, 0, 0, 0 },
100 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
101 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
102 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
103 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
104 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
105 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
106 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
107 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
108 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
109 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
110 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
111 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
112 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
113 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
114 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
115 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
116 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
117 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
118 },
119
120 /* Port C configuration */
121 { /* conf ppar psor pdir podr pdat */
122 /* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */
123 /* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */
124 /* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */
125 /* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */
126 /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */
127 /* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */
128 /* PC25 */ { 0, 0, 0, 1, 0, 0 },
129 /* PC24 */ { 0, 0, 0, 1, 0, 0 },
130 /* PC23 */ { 0, 1, 0, 1, 0, 0 },
131 /* PC22 */ { 0, 1, 0, 0, 0, 0 },
132 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
133 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
134 /* PC19 */ { 0, 1, 0, 0, 0, 0 },
135 /* PC18 */ { 0, 1, 0, 0, 0, 0 },
136 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
137 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
138 /* PC15 */ { 0, 0, 0, 1, 0, 0 },
139 /* PC14 */ { 0, 1, 0, 0, 0, 0 },
140 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
141 /* PC12 */ { 0, 0, 0, 1, 0, 0 },
142 /* PC11 */ { 0, 0, 0, 1, 0, 0 },
143 /* PC10 */ { 0, 0, 0, 1, 0, 0 },
144 /* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */
145 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */
146 /* PC7 */ { 0, 0, 0, 0, 0, 0 },
147 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */
148 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */
149 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */
150 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */
151 /* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */
152 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */
153 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */
154 },
155
156 /* Port D configuration */
157 { /* conf ppar psor pdir podr pdat */
158 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
159 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
160 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */
161 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */
162 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */
163 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */
164 /* PD25 */ { 0, 0, 0, 1, 0, 0 },
165 /* PD24 */ { 0, 0, 0, 1, 0, 0 },
166 /* PD23 */ { 0, 0, 0, 1, 0, 0 },
167 /* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */
168 /* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */
169 /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
170 /* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */
171 /* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */
172 /* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */
173 /* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */
174 #if defined(CONFIG_SOFT_I2C)
175 /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
176 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
177 #else
178 #if defined(CONFIG_HARD_I2C)
179 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
180 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
181 #else /* normal I/O port pins */
182 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
183 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
184 #endif
185 #endif
186 /* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */
187 /* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */
188 /* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */
189 /* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */
190 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
191 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
192 /* PD7 */ { 0, 0, 0, 1, 0, 1 },
193 /* PD6 */ { 0, 0, 0, 1, 0, 1 },
194 /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */
195 /* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */
196 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
197 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
198 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
199 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
200 }
201 };
202
203 /* ------------------------------------------------------------------------- */
204
205 /* Check Board Identity:
206 */
207 int checkboard (void)
208 {
209 unsigned char str[64];
210 int i = getenv_r ("serial#", str, sizeof (str));
211
212 puts ("Board: ");
213
214 if (!i || strncmp (str, "TQM8260", 7)) {
215 puts ("### No HW ID - assuming TQM8260\n");
216 return (0);
217 }
218
219 puts (str);
220 putc ('\n');
221
222 return 0;
223 }
224
225 /* ------------------------------------------------------------------------- */
226
227 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
228 *
229 * This routine performs standard 8260 initialization sequence
230 * and calculates the available memory size. It may be called
231 * several times to try different SDRAM configurations on both
232 * 60x and local buses.
233 */
234 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
235 ulong orx, volatile uchar * base)
236 {
237 volatile uchar c = 0xff;
238 ulong cnt, val;
239 volatile ulong *addr;
240 volatile uint *sdmr_ptr;
241 volatile uint *orx_ptr;
242 int i;
243 ulong save[32]; /* to make test non-destructive */
244 ulong maxsize;
245
246 /* We must be able to test a location outsize the maximum legal size
247 * to find out THAT we are outside; but this address still has to be
248 * mapped by the controller. That means, that the initial mapping has
249 * to be (at least) twice as large as the maximum expected size.
250 */
251 maxsize = (1 + (~orx | 0x7fff)) / 2;
252
253 /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
254 * we are configuring CS1 if base != 0
255 */
256 sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
257 orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
258
259 *orx_ptr = orx;
260
261 /*
262 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
263 *
264 * "At system reset, initialization software must set up the
265 * programmable parameters in the memory controller banks registers
266 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
267 * system software should execute the following initialization sequence
268 * for each SDRAM device.
269 *
270 * 1. Issue a PRECHARGE-ALL-BANKS command
271 * 2. Issue eight CBR REFRESH commands
272 * 3. Issue a MODE-SET command to initialize the mode register
273 *
274 * The initial commands are executed by setting P/LSDMR[OP] and
275 * accessing the SDRAM with a single-byte transaction."
276 *
277 * The appropriate BRx/ORx registers have already been set when we
278 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
279 */
280
281 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
282 *base = c;
283
284 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
285 for (i = 0; i < 8; i++)
286 *base = c;
287
288 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
289 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
290
291 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
292 *base = c;
293
294 /*
295 * Check memory range for valid RAM. A simple memory test determines
296 * the actually available RAM size between addresses `base' and
297 * `base + maxsize'. Some (not all) hardware errors are detected:
298 * - short between address lines
299 * - short between data lines
300 */
301 i = 0;
302 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
303 addr = (volatile ulong *) base + cnt; /* pointer arith! */
304 save[i++] = *addr;
305 *addr = ~cnt;
306 }
307
308 addr = (volatile ulong *) base;
309 save[i] = *addr;
310 *addr = 0;
311
312 if ((val = *addr) != 0) {
313 *addr = save[i];
314 return (0);
315 }
316
317 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
318 addr = (volatile ulong *) base + cnt; /* pointer arith! */
319 val = *addr;
320 *addr = save[--i];
321 if (val != ~cnt) {
322 /* Write the actual size to ORx
323 */
324 *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
325 return (cnt * sizeof (long));
326 }
327 }
328 return (maxsize);
329 }
330
331 /*
332 * Test Power-On-Reset.
333 */
334 int power_on_reset (void)
335 {
336 DECLARE_GLOBAL_DATA_PTR;
337
338 /* Test Reset Status Register */
339 return gd->reset_status & RSR_CSRS ? 0 : 1;
340 }
341
342 long int initdram (int board_type)
343 {
344 volatile immap_t *immap = (immap_t *) CFG_IMMR;
345 volatile memctl8260_t *memctl = &immap->im_memctl;
346
347 #ifndef CFG_RAMBOOT
348 long size8, size9;
349 #endif
350 long psize, lsize;
351
352 psize = 16 * 1024 * 1024;
353 lsize = 0;
354
355 memctl->memc_psrt = CFG_PSRT;
356 memctl->memc_mptpr = CFG_MPTPR;
357
358 #if 0 /* Just for debugging */
359 #define prt_br_or(brX,orX) do { \
360 ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
361 ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
362 printf ("\n" \
363 #brX " 0x%08x " #orX " 0x%08x " \
364 "==> 0x%08lx ... 0x%08lx = %ld MB\n", \
365 memctl->memc_ ## brX, memctl->memc_ ## orX, \
366 start, start+sizem, (sizem+1)>>20); \
367 } while (0)
368 prt_br_or (br0, or0);
369 prt_br_or (br1, or1);
370 prt_br_or (br2, or2);
371 prt_br_or (br3, or3);
372 #endif
373
374 #ifndef CFG_RAMBOOT
375 /* 60x SDRAM setup:
376 */
377 size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
378 (uchar *) CFG_SDRAM_BASE);
379 size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
380 (uchar *) CFG_SDRAM_BASE);
381
382 if (size8 < size9) {
383 psize = size9;
384 printf ("(60x:9COL - %ld MB, ", psize >> 20);
385 } else {
386 psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
387 (uchar *) CFG_SDRAM_BASE);
388 printf ("(60x:8COL - %ld MB, ", psize >> 20);
389 }
390
391 /* Local SDRAM setup:
392 */
393 #ifdef CFG_INIT_LOCAL_SDRAM
394 memctl->memc_lsrt = CFG_LSRT;
395 size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
396 (uchar *) SDRAM_BASE2_PRELIM);
397 size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
398 (uchar *) SDRAM_BASE2_PRELIM);
399
400 if (size8 < size9) {
401 lsize = size9;
402 printf ("Local:9COL - %ld MB) using ", lsize >> 20);
403 } else {
404 lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
405 (uchar *) SDRAM_BASE2_PRELIM);
406 printf ("Local:8COL - %ld MB) using ", lsize >> 20);
407 }
408
409 #if 0
410 /* Set up BR2 so that the local SDRAM goes
411 * right after the 60x SDRAM
412 */
413 memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
414 (CFG_SDRAM_BASE + psize);
415 #endif
416 #endif /* CFG_INIT_LOCAL_SDRAM */
417 #endif /* CFG_RAMBOOT */
418
419 icache_enable ();
420
421 config_scoh_cs ();
422
423 return (psize);
424 }
425
426 /* ------------------------------------------------------------------------- */
427
428 static void config_scoh_cs (void)
429 {
430 volatile immap_t *immr = (immap_t *) CFG_IMMR;
431 volatile memctl8260_t *memctl = &immr->im_memctl;
432 volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE;
433 volatile uint tmp, i;
434
435 /* Initialize OR3 / BR3 for CAN Bus Controller 0 */
436 memctl->memc_or3 = CFG_CAN0_OR3;
437 memctl->memc_br3 = CFG_CAN0_BR3;
438 /* Initialize OR4 / BR4 for CAN Bus Controller 1 */
439 memctl->memc_or4 = CFG_CAN1_OR4;
440 memctl->memc_br4 = CFG_CAN1_BR4;
441
442 /* Initialize MAMR to write in the array at address 0x0 */
443 memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
444
445 /* Initialize UPMA for CAN: single read */
446 memctl->memc_mdr = 0xcffeec00;
447 udelay (1); /* Necessary to have the data correct in the UPM array!!!! */
448 /* The read on the CAN controller write the data of mdr in UPMA array. */
449 /* The index to the array will be incremented automatically
450 through this read */
451 tmp = can->cpu_interface;
452
453 memctl->memc_mdr = 0x0ffcec00;
454 udelay (1);
455 tmp = can->cpu_interface;
456
457 memctl->memc_mdr = 0x0ffcec00;
458 udelay (1);
459 tmp = can->cpu_interface;
460
461 memctl->memc_mdr = 0x0ffcec00;
462 udelay (1);
463 tmp = can->cpu_interface;
464
465 memctl->memc_mdr = 0x0ffcec00;
466 udelay (1);
467 tmp = can->cpu_interface;
468
469 memctl->memc_mdr = 0x0ffcfc00;
470 udelay (1);
471 tmp = can->cpu_interface;
472
473 memctl->memc_mdr = 0x0ffcfc00;
474 udelay (1);
475 tmp = can->cpu_interface;
476
477 memctl->memc_mdr = 0xfffdec07;
478 udelay (1);
479 tmp = can->cpu_interface;
480
481
482 /* Initialize MAMR to write in the array at address 0x18 */
483 memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
484
485 /* Initialize UPMA for CAN: single write */
486 memctl->memc_mdr = 0xfcffec00;
487 udelay (1);
488 tmp = can->cpu_interface;
489
490 memctl->memc_mdr = 0x00ffec00;
491 udelay (1);
492 tmp = can->cpu_interface;
493
494 memctl->memc_mdr = 0x00ffec00;
495 udelay (1);
496 tmp = can->cpu_interface;
497
498 memctl->memc_mdr = 0x00ffec00;
499 udelay (1);
500 tmp = can->cpu_interface;
501
502 memctl->memc_mdr = 0x00ffec00;
503 udelay (1);
504 tmp = can->cpu_interface;
505
506 memctl->memc_mdr = 0x00fffc00;
507 udelay (1);
508 tmp = can->cpu_interface;
509
510 memctl->memc_mdr = 0x00fffc00;
511 udelay (1);
512 tmp = can->cpu_interface;
513
514 memctl->memc_mdr = 0x30ffec07;
515 udelay (1);
516 tmp = can->cpu_interface;
517
518 /* Initialize MAMR */
519 memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */
520
521
522 /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
523 memctl->memc_or5 = CFG_EXTPROM_OR5;
524 memctl->memc_br5 = CFG_EXTPROM_BR5;
525 /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
526 memctl->memc_or6 = CFG_EXTPROM_OR6;
527 memctl->memc_br6 = CFG_EXTPROM_BR6;
528
529 /* Initialize OR7 / BR7 for the Glue Logic */
530 memctl->memc_or7 = CFG_FIOX_OR7;
531 memctl->memc_br7 = CFG_FIOX_BR7;
532
533 /* Initialize OR8 / BR8 for the DOH Logic */
534 memctl->memc_or8 = CFG_FDOHM_OR8;
535 memctl->memc_br8 = CFG_FDOHM_BR8;
536
537 DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
538 DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
539 DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
540 DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
541 DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
542 DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
543 DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
544 DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
545 DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
546
547 DEBUGF ("UPMA addr 0x0\n");
548 memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
549 for (i = 0; i < 0x8; i++) {
550 tmp = can->cpu_interface;
551 udelay (1);
552 DEBUGF (" %08x ", memctl->memc_mdr);
553 }
554 DEBUGF ("\nUPMA addr 0x18\n");
555 memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
556 for (i = 0; i < 0x8; i++) {
557 tmp = can->cpu_interface;
558 udelay (1);
559 DEBUGF (" %08x ", memctl->memc_mdr);
560 }
561 DEBUGF ("\n");
562 memctl->memc_mamr = MxMR_GPL_x4DIS;
563 }
564
565 /* ------------------------------------------------------------------------- */
566
567 int misc_init_r (void)
568 {
569 fpga_init ();
570 return (0);
571 }
572
573 /* ------------------------------------------------------------------------- */
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