board/siemens/draco/board.c

   1 /*
   2  * Board functions for TI AM335X based draco board
   3  * (C) Copyright 2013 Siemens Schweiz AG
   4  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  *
   8  * Board functions for TI AM335X based boards
   9  * u-boot:/board/ti/am335x/board.c
  10  *
  11  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/arch/mem.h>
  28 #include <asm/io.h>
  29 #include <asm/emif.h>
  30 #include <asm/gpio.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36 #include "../common/factoryset.h"
  37 #include <nand.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #ifdef CONFIG_SPL_BUILD
  42 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
  43
  44 #if DDR_PLL_FREQ == 303
  45 #if !defined(CONFIG_TARGET_ETAMIN)
  46 /* Default@303MHz-i0 */
  47 const struct ddr3_data ddr3_default = {
  48         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  49         0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
  50         0x0000093B, 0x0000014A,
  51         "default name @303MHz           \0",
  52         "default marking                \0",
  53 };
  54 #else
  55 /* etamin board */
  56 const struct ddr3_data ddr3_default = {
  57         0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
  58         0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
  59         0x0000093B, 0x0000018A,
  60         "test-etamin                    \0",
  61         "generic-8Gbit                  \0",
  62 };
  63 #endif
  64 #elif DDR_PLL_FREQ == 400
  65 /* Default@400MHz-i0 */
  66 const struct ddr3_data ddr3_default = {
  67         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  68         0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  69         0x00000618, 0x0000014A,
  70         "default name @400MHz           \0",
  71         "default marking                \0",
  72 };
  73 #endif
  74
  75 static void set_default_ddr3_timings(void)
  76 {
  77         printf("Set default DDR3 settings\n");
  78         settings.ddr3 = ddr3_default;
  79 }
  80
  81 static void print_ddr3_timings(void)
  82 {
  83         printf("\nDDR3\n");
  84         printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  85         printf("device:\t\t%s\n", settings.ddr3.manu_name);
  86         printf("marking:\t%s\n", settings.ddr3.manu_marking);
  87         printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
  88                "default", "diff");
  89         PRINTARGS(magic);
  90         PRINTARGS(version);
  91         PRINTARGS(ddr3_sratio);
  92         PRINTARGS(iclkout);
  93
  94         PRINTARGS(dt0rdsratio0);
  95         PRINTARGS(dt0wdsratio0);
  96         PRINTARGS(dt0fwsratio0);
  97         PRINTARGS(dt0wrsratio0);
  98
  99         PRINTARGS(sdram_tim1);
 100         PRINTARGS(sdram_tim2);
 101         PRINTARGS(sdram_tim3);
 102
 103         PRINTARGS(emif_ddr_phy_ctlr_1);
 104
 105         PRINTARGS(sdram_config);
 106         PRINTARGS(ref_ctrl);
 107         PRINTARGS(ioctr_val);
 108 }
 109
 110 static void print_chip_data(void)
 111 {
 112         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 113         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 114         printf("\nCPU BOARD\n");
 115         printf("device: \t'%s'\n", settings.chip.sdevname);
 116         printf("hw version: \t'%s'\n", settings.chip.shwver);
 117         printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
 118 }
 119 #endif /* CONFIG_SPL_BUILD */
 120
 121 #define AM335X_NAND_ECC_MASK 0x0f
 122 #define AM335X_NAND_ECC_TYPE_16 0x02
 123
 124 static int ecc_type;
 125
 126 struct am335x_nand_geometry {
 127         u32 magic;
 128         u8 nand_geo_addr;
 129         u8 nand_geo_page;
 130         u8 nand_bus;
 131 };
 132
 133 static int draco_read_nand_geometry(void)
 134 {
 135         struct am335x_nand_geometry geo;
 136
 137         /* Read NAND geometry */
 138         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
 139                      (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
 140                 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
 141                 return -EIO;
 142         }
 143         if (geo.magic != 0xa657b310) {
 144                 printf("%s: bad magic: %x\n", __func__, geo.magic);
 145                 return -EFAULT;
 146         }
 147         if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
 148                 ecc_type = 16;
 149         else
 150                 ecc_type = 8;
 151
 152         return 0;
 153 }
 154
 155 /*
 156  * Read header information from EEPROM into global structure.
 157  */
 158 static int read_eeprom(void)
 159 {
 160         /* Check if baseboard eeprom is available */
 161         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 162                 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 163                 return 1;
 164         }
 165
 166 #ifdef CONFIG_SPL_BUILD
 167         /* Read Siemens eeprom data (DDR3) */
 168         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 169                      (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 170                 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 171                 set_default_ddr3_timings();
 172         }
 173         /* Read Siemens eeprom data (CHIP) */
 174         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 175                      (uchar *)&settings.chip, sizeof(settings.chip)))
 176                 printf("Could not read chip settings\n");
 177
 178         if (ddr3_default.magic == settings.ddr3.magic &&
 179             ddr3_default.version == settings.ddr3.version) {
 180                 printf("Using DDR3 settings from EEPROM\n");
 181         } else {
 182                 if (ddr3_default.magic != settings.ddr3.magic)
 183                         printf("Warning: No valid DDR3 data in eeprom.\n");
 184                 if (ddr3_default.version != settings.ddr3.version)
 185                         printf("Warning: DDR3 data version does not match.\n");
 186
 187                 printf("Using default settings\n");
 188                 set_default_ddr3_timings();
 189         }
 190
 191         if (MAGIC_CHIP == settings.chip.magic)
 192                 print_chip_data();
 193         else
 194                 printf("Warning: No chip data in eeprom\n");
 195
 196         print_ddr3_timings();
 197
 198         return draco_read_nand_geometry();
 199 #endif
 200         return 0;
 201 }
 202
 203 #ifdef CONFIG_SPL_BUILD
 204 static void board_init_ddr(void)
 205 {
 206 struct emif_regs draco_ddr3_emif_reg_data = {
 207         .zq_config = 0x50074BE4,
 208 };
 209
 210 struct ddr_data draco_ddr3_data = {
 211 };
 212
 213 struct cmd_control draco_ddr3_cmd_ctrl_data = {
 214 };
 215
 216 struct ctrl_ioregs draco_ddr3_ioregs = {
 217 };
 218
 219         /* pass values from eeprom */
 220         draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 221         draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
 222         draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
 223         draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 224                 settings.ddr3.emif_ddr_phy_ctlr_1;
 225         draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
 226         draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
 227         draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 228
 229         draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
 230         draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
 231         draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
 232         draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
 233
 234         draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
 235         draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
 236         draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
 237         draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
 238         draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 239         draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 240
 241         draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
 242         draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
 243         draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
 244         draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
 245         draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
 246
 247         config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
 248                    &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
 249 }
 250
 251 static void spl_siemens_board_init(void)
 252 {
 253         return;
 254 }
 255 #endif /* if def CONFIG_SPL_BUILD */
 256
 257 #ifdef CONFIG_BOARD_LATE_INIT
 258 int board_late_init(void)
 259 {
 260         int ret;
 261
 262         ret = draco_read_nand_geometry();
 263         if (ret != 0)
 264                 return ret;
 265
 266         nand_curr_device = 0;
 267         omap_nand_switch_ecc(1, ecc_type);
 268 #ifdef CONFIG_TARGET_ETAMIN
 269         nand_curr_device = 1;
 270         omap_nand_switch_ecc(1, ecc_type);
 271 #endif
 272 #ifdef CONFIG_FACTORYSET
 273         /* Set ASN in environment*/
 274         if (factory_dat.asn[0] != 0) {
 275                 env_set("dtb_name", (char *)factory_dat.asn);
 276         } else {
 277                 /* dtb suffix gets added in load script */
 278                 env_set("dtb_name", "am335x-draco");
 279         }
 280 #else
 281         env_set("dtb_name", "am335x-draco");
 282 #endif
 283
 284         return 0;
 285 }
 286 #endif
 287
 288 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 289         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 290 static void cpsw_control(int enabled)
 291 {
 292         /* VTP can be added here */
 293
 294         return;
 295 }
 296
 297 static struct cpsw_slave_data cpsw_slaves[] = {
 298         {
 299                 .slave_reg_ofs  = 0x208,
 300                 .sliver_reg_ofs = 0xd80,
 301                 .phy_addr       = 0,
 302                 .phy_if         = PHY_INTERFACE_MODE_MII,
 303         },
 304 };
 305
 306 static struct cpsw_platform_data cpsw_data = {
 307         .mdio_base              = CPSW_MDIO_BASE,
 308         .cpsw_base              = CPSW_BASE,
 309         .mdio_div               = 0xff,
 310         .channels               = 4,
 311         .cpdma_reg_ofs          = 0x800,
 312         .slaves                 = 1,
 313         .slave_data             = cpsw_slaves,
 314         .ale_reg_ofs            = 0xd00,
 315         .ale_entries            = 1024,
 316         .host_port_reg_ofs      = 0x108,
 317         .hw_stats_reg_ofs       = 0x900,
 318         .bd_ram_ofs             = 0x2000,
 319         .mac_control            = (1 << 5),
 320         .control                = cpsw_control,
 321         .host_port_num          = 0,
 322         .version                = CPSW_CTRL_VERSION_2,
 323 };
 324
 325 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 326         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 327 int board_eth_init(bd_t *bis)
 328 {
 329         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 330         int n = 0;
 331         int rv;
 332
 333         factoryset_env_set();
 334
 335         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 336         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 337
 338         rv = cpsw_register(&cpsw_data);
 339         if (rv < 0)
 340                 printf("Error %d registering CPSW switch\n", rv);
 341         else
 342                 n += rv;
 343         return n;
 344 }
 345
 346 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
 347                           char *const argv[])
 348 {
 349         /* Reset SMSC LAN9303 switch for default configuration */
 350         gpio_request(GPIO_LAN9303_NRST, "nRST");
 351         gpio_direction_output(GPIO_LAN9303_NRST, 0);
 352         /* assert active low reset for 200us */
 353         udelay(200);
 354         gpio_set_value(GPIO_LAN9303_NRST, 1);
 355
 356         return 0;
 357 };
 358
 359 U_BOOT_CMD(
 360         switch_rst, CONFIG_SYS_MAXARGS, 1,      do_switch_reset,
 361         "Reset LAN9303 switch via its reset pin",
 362         ""
 363 );
 364 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 365 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 366
 367 #ifdef CONFIG_NAND_CS_INIT
 368 /* GPMC definitions for second nand cs1 */
 369 static const u32 gpmc_nand_config[] = {
 370         ETAMIN_NAND_GPMC_CONFIG1,
 371         ETAMIN_NAND_GPMC_CONFIG2,
 372         ETAMIN_NAND_GPMC_CONFIG3,
 373         ETAMIN_NAND_GPMC_CONFIG4,
 374         ETAMIN_NAND_GPMC_CONFIG5,
 375         ETAMIN_NAND_GPMC_CONFIG6,
 376         /*CONFIG7- computed as params */
 377 };
 378
 379 static void board_nand_cs_init(void)
 380 {
 381         enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
 382                               0x18000000, GPMC_SIZE_16M);
 383 }
 384 #endif
 385
 386 #include "../common/board.c"