2 * Board functions for TI AM335X based dxr2 board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * Board functions for TI AM335X based boards
9 * u-boot:/board/ti/am335x/board.c
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/omap.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/sys_proto.h>
35 #include "../common/factoryset.h"
37 DECLARE_GLOBAL_DATA_PTR
;
39 #ifdef CONFIG_SPL_BUILD
40 static struct dxr2_baseboard_id
__attribute__((section(".data"))) settings
;
42 const struct ddr3_data ddr3_default
= {
43 0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
44 0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
45 0x00000618, 0x0000014A,
48 static void set_default_ddr3_timings(void)
50 printf("Set default DDR3 settings\n");
51 settings
.ddr3
= ddr3_default
;
54 static void print_ddr3_timings(void)
56 printf("\n\nDDR3 Timing parameters:\n");
57 printf("Diff Eeprom Default\n");
60 PRINTARGS(ddr3_sratio
);
63 PRINTARGS(dt0rdsratio0
);
64 PRINTARGS(dt0wdsratio0
);
65 PRINTARGS(dt0fwsratio0
);
66 PRINTARGS(dt0wrsratio0
);
68 PRINTARGS(sdram_tim1
);
69 PRINTARGS(sdram_tim2
);
70 PRINTARGS(sdram_tim3
);
72 PRINTARGS(emif_ddr_phy_ctlr_1
);
74 PRINTARGS(sdram_config
);
79 static void print_chip_data(void)
82 printf("Device: '%s'\n", settings
.chip
.sdevname
);
83 printf("HW version: '%s'\n", settings
.chip
.shwver
);
85 #endif /* CONFIG_SPL_BUILD */
88 * Read header information from EEPROM into global structure.
90 static int read_eeprom(void)
92 /* Check if baseboard eeprom is available */
93 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR
)) {
94 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
98 #ifdef CONFIG_SPL_BUILD
99 /* Read Siemens eeprom data (DDR3) */
100 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, EEPROM_ADDR_DDR3
, 2,
101 (uchar
*)&settings
.ddr3
, sizeof(struct ddr3_data
))) {
102 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
103 set_default_ddr3_timings();
105 /* Read Siemens eeprom data (CHIP) */
106 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR
, EEPROM_ADDR_CHIP
, 2,
107 (uchar
*)&settings
.chip
, sizeof(settings
.chip
)))
108 printf("Could not read chip settings\n");
110 if (ddr3_default
.magic
== settings
.ddr3
.magic
&&
111 ddr3_default
.version
== settings
.ddr3
.version
) {
112 printf("Using DDR3 settings from EEPROM\n");
114 if (ddr3_default
.magic
!= settings
.ddr3
.magic
)
115 printf("Error: No valid DDR3 data in eeprom.\n");
116 if (ddr3_default
.version
!= settings
.ddr3
.version
)
117 printf("Error: DDR3 data version does not match.\n");
119 printf("Using default settings\n");
120 set_default_ddr3_timings();
123 if (MAGIC_CHIP
== settings
.chip
.magic
) {
124 printf("Valid chip data in eeprom\n");
127 printf("Error: No chip data in eeprom\n");
130 print_ddr3_timings();
135 #ifdef CONFIG_SPL_BUILD
136 static void board_init_ddr(void)
138 struct emif_regs dxr2_ddr3_emif_reg_data
= {
139 .zq_config
= 0x50074BE4,
142 struct ddr_data dxr2_ddr3_data
= {
145 struct cmd_control dxr2_ddr3_cmd_ctrl_data
= {
148 struct ctrl_ioregs dxr2_ddr3_ioregs
= {
151 /* pass values from eeprom */
152 dxr2_ddr3_emif_reg_data
.sdram_tim1
= settings
.ddr3
.sdram_tim1
;
153 dxr2_ddr3_emif_reg_data
.sdram_tim2
= settings
.ddr3
.sdram_tim2
;
154 dxr2_ddr3_emif_reg_data
.sdram_tim3
= settings
.ddr3
.sdram_tim3
;
155 dxr2_ddr3_emif_reg_data
.emif_ddr_phy_ctlr_1
=
156 settings
.ddr3
.emif_ddr_phy_ctlr_1
;
157 dxr2_ddr3_emif_reg_data
.sdram_config
= settings
.ddr3
.sdram_config
;
158 dxr2_ddr3_emif_reg_data
.ref_ctrl
= settings
.ddr3
.ref_ctrl
;
160 dxr2_ddr3_data
.datardsratio0
= settings
.ddr3
.dt0rdsratio0
;
161 dxr2_ddr3_data
.datawdsratio0
= settings
.ddr3
.dt0wdsratio0
;
162 dxr2_ddr3_data
.datafwsratio0
= settings
.ddr3
.dt0fwsratio0
;
163 dxr2_ddr3_data
.datawrsratio0
= settings
.ddr3
.dt0wrsratio0
;
165 dxr2_ddr3_cmd_ctrl_data
.cmd0csratio
= settings
.ddr3
.ddr3_sratio
;
166 dxr2_ddr3_cmd_ctrl_data
.cmd0iclkout
= settings
.ddr3
.iclkout
;
167 dxr2_ddr3_cmd_ctrl_data
.cmd1csratio
= settings
.ddr3
.ddr3_sratio
;
168 dxr2_ddr3_cmd_ctrl_data
.cmd1iclkout
= settings
.ddr3
.iclkout
;
169 dxr2_ddr3_cmd_ctrl_data
.cmd2csratio
= settings
.ddr3
.ddr3_sratio
;
170 dxr2_ddr3_cmd_ctrl_data
.cmd2iclkout
= settings
.ddr3
.iclkout
;
172 dxr2_ddr3_ioregs
.cm0ioctl
= settings
.ddr3
.ioctr_val
,
173 dxr2_ddr3_ioregs
.cm1ioctl
= settings
.ddr3
.ioctr_val
,
174 dxr2_ddr3_ioregs
.cm2ioctl
= settings
.ddr3
.ioctr_val
,
175 dxr2_ddr3_ioregs
.dt0ioctl
= settings
.ddr3
.ioctr_val
,
176 dxr2_ddr3_ioregs
.dt1ioctl
= settings
.ddr3
.ioctr_val
,
178 config_ddr(DDR_PLL_FREQ
, &dxr2_ddr3_ioregs
, &dxr2_ddr3_data
,
179 &dxr2_ddr3_cmd_ctrl_data
, &dxr2_ddr3_emif_reg_data
, 0);
182 static void spl_siemens_board_init(void)
186 #endif /* if def CONFIG_SPL_BUILD */
188 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
189 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
190 static void cpsw_control(int enabled
)
192 /* VTP can be added here */
197 static struct cpsw_slave_data cpsw_slaves
[] = {
199 .slave_reg_ofs
= 0x208,
200 .sliver_reg_ofs
= 0xd80,
202 .phy_if
= PHY_INTERFACE_MODE_MII
,
206 static struct cpsw_platform_data cpsw_data
= {
207 .mdio_base
= CPSW_MDIO_BASE
,
208 .cpsw_base
= CPSW_BASE
,
211 .cpdma_reg_ofs
= 0x800,
213 .slave_data
= cpsw_slaves
,
214 .ale_reg_ofs
= 0xd00,
216 .host_port_reg_ofs
= 0x108,
217 .hw_stats_reg_ofs
= 0x900,
218 .bd_ram_ofs
= 0x2000,
219 .mac_control
= (1 << 5),
220 .control
= cpsw_control
,
222 .version
= CPSW_CTRL_VERSION_2
,
225 #if defined(CONFIG_DRIVER_TI_CPSW) || \
226 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
227 int board_eth_init(bd_t
*bis
)
229 struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
235 /* Set rgmii mode and enable rmii clock to be sourced from chip */
236 writel((RMII_MODE_ENABLE
| RMII_CHIPCKL_ENABLE
), &cdev
->miisel
);
238 rv
= cpsw_register(&cpsw_data
);
240 printf("Error %d registering CPSW switch\n", rv
);
246 static int do_switch_reset(cmd_tbl_t
*cmdtp
, int flag
, int argc
,
249 /* Reset SMSC LAN9303 switch for default configuration */
250 gpio_request(GPIO_LAN9303_NRST
, "nRST");
251 gpio_direction_output(GPIO_LAN9303_NRST
, 0);
252 /* assert active low reset for 200us */
254 gpio_set_value(GPIO_LAN9303_NRST
, 1);
260 switch_rst
, CONFIG_SYS_MAXARGS
, 1, do_switch_reset
,
261 "Reset LAN9303 switch via its reset pin",
264 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
265 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
267 #include "../common/board.c"