2 * pinmux setup for siemens dxr2 board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * u-boot:/board/ti/am335x/mux.c
9 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/mux.h>
22 static struct module_pin_mux uart0_pin_mux
[] = {
23 {OFFSET(uart0_rxd
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* UART0_RXD */
24 {OFFSET(uart0_txd
), (MODE(0) | PULLUDEN
)}, /* UART0_TXD */
28 static struct module_pin_mux uart3_pin_mux
[] = {
29 {OFFSET(spi0_cs1
), (MODE(1) | PULLUP_EN
| RXACTIVE
)}, /* UART3_RXD */
30 {OFFSET(ecap0_in_pwm0_out
), (MODE(1) | PULLUDEN
)}, /* UART3_TXD */
34 static struct module_pin_mux i2c0_pin_mux
[] = {
35 {OFFSET(i2c0_sda
), (MODE(0) | RXACTIVE
|
36 PULLUDEN
| SLEWCTRL
)}, /* I2C_DATA */
37 {OFFSET(i2c0_scl
), (MODE(0) | RXACTIVE
|
38 PULLUDEN
| SLEWCTRL
)}, /* I2C_SCLK */
42 static struct module_pin_mux nand_pin_mux
[] = {
43 {OFFSET(gpmc_ad0
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD0 */
44 {OFFSET(gpmc_ad1
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD1 */
45 {OFFSET(gpmc_ad2
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD2 */
46 {OFFSET(gpmc_ad3
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD3 */
47 {OFFSET(gpmc_ad4
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD4 */
48 {OFFSET(gpmc_ad5
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD5 */
49 {OFFSET(gpmc_ad6
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD6 */
50 {OFFSET(gpmc_ad7
), (MODE(0) | PULLUP_EN
| RXACTIVE
)}, /* NAND AD7 */
51 {OFFSET(gpmc_wait0
), (MODE(0) | RXACTIVE
| PULLUP_EN
)}, /* NAND WAIT */
52 {OFFSET(gpmc_wpn
), (MODE(7) | PULLUP_EN
| RXACTIVE
)}, /* NAND_WPN */
53 {OFFSET(gpmc_csn0
), (MODE(0) | PULLUDEN
)}, /* NAND_CS0 */
54 {OFFSET(gpmc_advn_ale
), (MODE(0) | PULLUDEN
)}, /* NAND_ADV_ALE */
55 {OFFSET(gpmc_oen_ren
), (MODE(0) | PULLUDEN
)}, /* NAND_OE */
56 {OFFSET(gpmc_wen
), (MODE(0) | PULLUDEN
)}, /* NAND_WEN */
57 {OFFSET(gpmc_be0n_cle
), (MODE(0) | PULLUDEN
)}, /* NAND_BE_CLE */
61 static struct module_pin_mux gpios_pin_mux
[] = {
62 /* DFU button GPIO0_27*/
63 {OFFSET(gpmc_ad11
), (MODE(7) | PULLUDEN
| RXACTIVE
)},
64 {OFFSET(gpmc_csn3
), MODE(7) }, /* LED0 GPIO2_0 */
65 {OFFSET(emu0
), MODE(7)}, /* LED1 GPIO3_7 */
66 /* Triacs in HW Rev 2 */
67 {OFFSET(uart1_ctsn
), MODE(7) | PULLUDDIS
| RXACTIVE
}, /* Y5 GPIO0_12*/
68 {OFFSET(mmc0_dat1
), MODE(7) | PULLUDDIS
| RXACTIVE
}, /* Y3 GPIO2_28*/
69 {OFFSET(mmc0_dat2
), MODE(7) | PULLUDDIS
| RXACTIVE
}, /* Y7 GPIO2_27*/
70 /* Triacs initial HW Rev */
71 {OFFSET(gpmc_csn1
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 1_30 Y0 */
72 {OFFSET(gpmc_be1n
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 1_28 Y1 */
73 {OFFSET(gpmc_csn2
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 1_31 Y2 */
74 {OFFSET(lcd_data15
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 0_11 Y3 */
75 {OFFSET(lcd_data14
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 0_10 Y4 */
76 {OFFSET(gpmc_clk
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 2_1 Y5 */
77 {OFFSET(emu1
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 3_8 Y6 */
78 {OFFSET(gpmc_ad15
), MODE(7) | RXACTIVE
| PULLUDDIS
}, /* 1_15 Y7 */
79 /* Remaining pins that were not used in this file */
80 {OFFSET(gpmc_ad8
), MODE(7) | RXACTIVE
| PULLUDDIS
},
81 {OFFSET(gpmc_ad9
), MODE(7) | RXACTIVE
| PULLUDDIS
},
82 {OFFSET(gpmc_a0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
83 {OFFSET(gpmc_a1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
84 {OFFSET(gpmc_a2
), MODE(7) | RXACTIVE
| PULLUDDIS
},
85 {OFFSET(gpmc_a3
), MODE(7) | RXACTIVE
| PULLUDDIS
},
86 {OFFSET(gpmc_a4
), MODE(7) | RXACTIVE
| PULLUDDIS
},
87 {OFFSET(gpmc_a5
), MODE(7) | RXACTIVE
| PULLUDDIS
},
88 {OFFSET(gpmc_a6
), MODE(7) | RXACTIVE
| PULLUDDIS
},
89 {OFFSET(gpmc_a7
), MODE(7) | RXACTIVE
| PULLUDDIS
},
90 {OFFSET(gpmc_a8
), MODE(7) | RXACTIVE
| PULLUDDIS
},
91 {OFFSET(gpmc_a9
), MODE(7) | RXACTIVE
| PULLUDDIS
},
92 {OFFSET(gpmc_a10
), MODE(7) | RXACTIVE
| PULLUDDIS
},
93 {OFFSET(gpmc_a11
), MODE(7) | RXACTIVE
| PULLUDDIS
},
94 {OFFSET(lcd_data0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
95 {OFFSET(lcd_data2
), MODE(7) | RXACTIVE
| PULLUDDIS
},
96 {OFFSET(lcd_data3
), MODE(7) | RXACTIVE
| PULLUDDIS
},
97 {OFFSET(lcd_data4
), MODE(7) | RXACTIVE
| PULLUDDIS
},
98 {OFFSET(lcd_data5
), MODE(7) | RXACTIVE
| PULLUDDIS
},
99 {OFFSET(lcd_data6
), MODE(7) | RXACTIVE
| PULLUDDIS
},
100 {OFFSET(lcd_data7
), MODE(7) | RXACTIVE
| PULLUDDIS
},
101 {OFFSET(lcd_data8
), MODE(7) | RXACTIVE
| PULLUDDIS
},
102 {OFFSET(lcd_data9
), MODE(7) | RXACTIVE
| PULLUDDIS
},
103 {OFFSET(lcd_vsync
), MODE(7) | RXACTIVE
| PULLUDDIS
},
104 {OFFSET(lcd_hsync
), MODE(7) | RXACTIVE
| PULLUDDIS
},
105 {OFFSET(lcd_pclk
), MODE(7) | RXACTIVE
| PULLUDDIS
},
106 {OFFSET(lcd_ac_bias_en
), MODE(7) | RXACTIVE
| PULLUDDIS
},
107 {OFFSET(mmc0_dat3
), MODE(7) | RXACTIVE
| PULLUDDIS
},
108 {OFFSET(mmc0_dat0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
109 {OFFSET(mmc0_clk
), MODE(7) | RXACTIVE
| PULLUDDIS
},
110 {OFFSET(mmc0_cmd
), MODE(7) | RXACTIVE
| PULLUDDIS
},
111 {OFFSET(spi0_sclk
), MODE(7) | RXACTIVE
| PULLUDDIS
},
112 {OFFSET(spi0_d0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
113 {OFFSET(spi0_d1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
114 {OFFSET(spi0_cs0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
115 {OFFSET(uart0_ctsn
), MODE(7) | RXACTIVE
| PULLUDDIS
},
116 {OFFSET(uart0_rtsn
), MODE(7) | RXACTIVE
| PULLUDDIS
},
117 {OFFSET(uart1_rtsn
), MODE(7) | RXACTIVE
| PULLUDDIS
},
118 {OFFSET(uart1_rxd
), MODE(7) | RXACTIVE
| PULLUDDIS
},
119 {OFFSET(uart1_txd
), MODE(7) | RXACTIVE
| PULLUDDIS
},
120 {OFFSET(mcasp0_aclkx
), MODE(7) | RXACTIVE
| PULLUDDIS
},
121 {OFFSET(mcasp0_fsx
), MODE(7) | RXACTIVE
| PULLUDDIS
},
122 {OFFSET(mcasp0_axr0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
123 {OFFSET(mcasp0_ahclkr
), MODE(7) | RXACTIVE
| PULLUDDIS
},
124 {OFFSET(mcasp0_aclkr
), MODE(7) | RXACTIVE
| PULLUDDIS
},
125 {OFFSET(mcasp0_fsr
), MODE(7) | RXACTIVE
| PULLUDDIS
},
126 {OFFSET(mcasp0_axr1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
127 {OFFSET(mcasp0_ahclkx
), MODE(7) | RXACTIVE
| PULLUDDIS
},
128 {OFFSET(xdma_event_intr0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
129 {OFFSET(xdma_event_intr1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
130 {OFFSET(nresetin_out
), MODE(7) | RXACTIVE
| PULLUDDIS
},
131 {OFFSET(porz
), MODE(7) | RXACTIVE
| PULLUDDIS
},
132 {OFFSET(nnmi
), MODE(7) | RXACTIVE
| PULLUDDIS
},
133 {OFFSET(osc0_in
), MODE(7) | RXACTIVE
| PULLUDDIS
},
134 {OFFSET(osc0_out
), MODE(7) | RXACTIVE
| PULLUDDIS
},
135 {OFFSET(rsvd1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
136 {OFFSET(tms
), MODE(7) | RXACTIVE
| PULLUDDIS
},
137 {OFFSET(tdi
), MODE(7) | RXACTIVE
| PULLUDDIS
},
138 {OFFSET(tdo
), MODE(7) | RXACTIVE
| PULLUDDIS
},
139 {OFFSET(tck
), MODE(7) | RXACTIVE
| PULLUDDIS
},
140 {OFFSET(ntrst
), MODE(7) | RXACTIVE
| PULLUDDIS
},
141 {OFFSET(osc1_in
), MODE(7) | RXACTIVE
| PULLUDDIS
},
142 {OFFSET(osc1_out
), MODE(7) | RXACTIVE
| PULLUDDIS
},
143 {OFFSET(pmic_power_en
), MODE(7) | RXACTIVE
| PULLUDDIS
},
144 {OFFSET(rtc_porz
), MODE(7) | RXACTIVE
| PULLUDDIS
},
145 {OFFSET(rsvd2
), MODE(7) | RXACTIVE
| PULLUDDIS
},
146 {OFFSET(ext_wakeup
), MODE(7) | RXACTIVE
| PULLUDDIS
},
147 {OFFSET(enz_kaldo_1p8v
), MODE(7) | RXACTIVE
| PULLUDDIS
},
148 {OFFSET(usb0_dm
), MODE(7) | RXACTIVE
| PULLUDDIS
},
149 {OFFSET(usb0_dp
), MODE(7) | RXACTIVE
| PULLUDDIS
},
150 {OFFSET(usb0_ce
), MODE(7) | RXACTIVE
| PULLUDDIS
},
151 {OFFSET(usb0_id
), MODE(7) | RXACTIVE
| PULLUDDIS
},
152 {OFFSET(usb0_vbus
), MODE(7) | RXACTIVE
| PULLUDDIS
},
153 {OFFSET(usb0_drvvbus
), MODE(7) | RXACTIVE
| PULLUDDIS
},
154 {OFFSET(usb1_dm
), MODE(7) | RXACTIVE
| PULLUDDIS
},
155 {OFFSET(usb1_dp
), MODE(7) | RXACTIVE
| PULLUDDIS
},
156 {OFFSET(usb1_ce
), MODE(7) | RXACTIVE
| PULLUDDIS
},
157 {OFFSET(usb1_id
), MODE(7) | RXACTIVE
| PULLUDDIS
},
158 {OFFSET(usb1_vbus
), MODE(7) | RXACTIVE
| PULLUDDIS
},
159 {OFFSET(usb1_drvvbus
), MODE(7) | RXACTIVE
| PULLUDDIS
},
160 {OFFSET(ddr_resetn
), MODE(7) | RXACTIVE
| PULLUDDIS
},
161 {OFFSET(ddr_csn0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
162 {OFFSET(ddr_cke
), MODE(7) | RXACTIVE
| PULLUDDIS
},
163 {OFFSET(ddr_ck
), MODE(7) | RXACTIVE
| PULLUDDIS
},
164 {OFFSET(ddr_nck
), MODE(7) | RXACTIVE
| PULLUDDIS
},
165 {OFFSET(ddr_casn
), MODE(7) | RXACTIVE
| PULLUDDIS
},
166 {OFFSET(ddr_rasn
), MODE(7) | RXACTIVE
| PULLUDDIS
},
167 {OFFSET(ddr_wen
), MODE(7) | RXACTIVE
| PULLUDDIS
},
168 {OFFSET(ddr_ba0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
169 {OFFSET(ddr_ba1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
170 {OFFSET(ddr_ba2
), MODE(7) | RXACTIVE
| PULLUDDIS
},
171 {OFFSET(ddr_a0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
172 {OFFSET(ddr_a1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
173 {OFFSET(ddr_a2
), MODE(7) | RXACTIVE
| PULLUDDIS
},
174 {OFFSET(ddr_a3
), MODE(7) | RXACTIVE
| PULLUDDIS
},
175 {OFFSET(ddr_a4
), MODE(7) | RXACTIVE
| PULLUDDIS
},
176 {OFFSET(ddr_a5
), MODE(7) | RXACTIVE
| PULLUDDIS
},
177 {OFFSET(ddr_a6
), MODE(7) | RXACTIVE
| PULLUDDIS
},
178 {OFFSET(ddr_a7
), MODE(7) | RXACTIVE
| PULLUDDIS
},
179 {OFFSET(ddr_a8
), MODE(7) | RXACTIVE
| PULLUDDIS
},
180 {OFFSET(ddr_a9
), MODE(7) | RXACTIVE
| PULLUDDIS
},
181 {OFFSET(ddr_a10
), MODE(7) | RXACTIVE
| PULLUDDIS
},
182 {OFFSET(ddr_a11
), MODE(7) | RXACTIVE
| PULLUDDIS
},
183 {OFFSET(ddr_a12
), MODE(7) | RXACTIVE
| PULLUDDIS
},
184 {OFFSET(ddr_a13
), MODE(7) | RXACTIVE
| PULLUDDIS
},
185 {OFFSET(ddr_a14
), MODE(7) | RXACTIVE
| PULLUDDIS
},
186 {OFFSET(ddr_a15
), MODE(7) | RXACTIVE
| PULLUDDIS
},
187 {OFFSET(ddr_odt
), MODE(7) | RXACTIVE
| PULLUDDIS
},
188 {OFFSET(ddr_d0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
189 {OFFSET(ddr_d1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
190 {OFFSET(ddr_d2
), MODE(7) | RXACTIVE
| PULLUDDIS
},
191 {OFFSET(ddr_d3
), MODE(7) | RXACTIVE
| PULLUDDIS
},
192 {OFFSET(ddr_d4
), MODE(7) | RXACTIVE
| PULLUDDIS
},
193 {OFFSET(ddr_d5
), MODE(7) | RXACTIVE
| PULLUDDIS
},
194 {OFFSET(ddr_d6
), MODE(7) | RXACTIVE
| PULLUDDIS
},
195 {OFFSET(ddr_d7
), MODE(7) | RXACTIVE
| PULLUDDIS
},
196 {OFFSET(ddr_d8
), MODE(7) | RXACTIVE
| PULLUDDIS
},
197 {OFFSET(ddr_d9
), MODE(7) | RXACTIVE
| PULLUDDIS
},
198 {OFFSET(ddr_d10
), MODE(7) | RXACTIVE
| PULLUDDIS
},
199 {OFFSET(ddr_d11
), MODE(7) | RXACTIVE
| PULLUDDIS
},
200 {OFFSET(ddr_d12
), MODE(7) | RXACTIVE
| PULLUDDIS
},
201 {OFFSET(ddr_d13
), MODE(7) | RXACTIVE
| PULLUDDIS
},
202 {OFFSET(ddr_d14
), MODE(7) | RXACTIVE
| PULLUDDIS
},
203 {OFFSET(ddr_d15
), MODE(7) | RXACTIVE
| PULLUDDIS
},
204 {OFFSET(ddr_dqm0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
205 {OFFSET(ddr_dqm1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
206 {OFFSET(ddr_dqs0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
207 {OFFSET(ddr_dqsn0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
208 {OFFSET(ddr_dqs1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
209 {OFFSET(ddr_dqsn1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
210 {OFFSET(ddr_vref
), MODE(7) | RXACTIVE
| PULLUDDIS
},
211 {OFFSET(ddr_vtp
), MODE(7) | RXACTIVE
| PULLUDDIS
},
212 {OFFSET(ddr_strben0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
213 {OFFSET(ddr_strben1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
214 {OFFSET(ain7
), MODE(7) | RXACTIVE
| PULLUDDIS
},
215 {OFFSET(ain6
), MODE(7) | RXACTIVE
| PULLUDDIS
},
216 {OFFSET(ain5
), MODE(7) | RXACTIVE
| PULLUDDIS
},
217 {OFFSET(ain4
), MODE(7) | RXACTIVE
| PULLUDDIS
},
218 {OFFSET(ain3
), MODE(7) | RXACTIVE
| PULLUDDIS
},
219 {OFFSET(ain2
), MODE(7) | RXACTIVE
| PULLUDDIS
},
220 {OFFSET(ain1
), MODE(7) | RXACTIVE
| PULLUDDIS
},
221 {OFFSET(ain0
), MODE(7) | RXACTIVE
| PULLUDDIS
},
222 {OFFSET(vrefp
), MODE(7) | RXACTIVE
| PULLUDDIS
},
223 {OFFSET(vrefn
), MODE(7) | RXACTIVE
| PULLUDDIS
},
224 /* nRST for SMSC LAN9303 switch - GPIO2_24 */
225 {OFFSET(lcd_pclk
), MODE(7) }, /* LAN9303 nRST */
229 static struct module_pin_mux ethernet_pin_mux
[] = {
230 {OFFSET(mii1_col
), (MODE(3) | RXACTIVE
)},
231 {OFFSET(mii1_crs
), (MODE(1) | RXACTIVE
)},
232 {OFFSET(mii1_rxerr
), (MODE(1) | RXACTIVE
)},
233 {OFFSET(mii1_txen
), (MODE(1))},
234 {OFFSET(mii1_rxdv
), (MODE(3) | RXACTIVE
)},
235 {OFFSET(mii1_txd3
), (MODE(7) | RXACTIVE
)},
236 {OFFSET(mii1_txd2
), (MODE(7) | RXACTIVE
)},
237 {OFFSET(mii1_txd1
), (MODE(1))},
238 {OFFSET(mii1_txd0
), (MODE(1))},
239 {OFFSET(mii1_txclk
), (MODE(1) | RXACTIVE
)},
240 {OFFSET(mii1_rxclk
), (MODE(1) | RXACTIVE
)},
241 {OFFSET(mii1_rxd3
), (MODE(1) | RXACTIVE
)},
242 {OFFSET(mii1_rxd2
), (MODE(1))},
243 {OFFSET(mii1_rxd1
), (MODE(1) | RXACTIVE
)},
244 {OFFSET(mii1_rxd0
), (MODE(1) | RXACTIVE
)},
245 {OFFSET(rmii1_refclk
), (MODE(0) | RXACTIVE
)},
246 {OFFSET(mdio_data
), (MODE(0) | RXACTIVE
| PULLUP_EN
)},
247 {OFFSET(mdio_clk
), (MODE(0) | PULLUP_EN
)},
251 void enable_uart0_pin_mux(void)
253 configure_module_pin_mux(uart0_pin_mux
);
256 void enable_uart3_pin_mux(void)
258 configure_module_pin_mux(uart3_pin_mux
);
261 void enable_i2c0_pin_mux(void)
263 configure_module_pin_mux(i2c0_pin_mux
);
266 void enable_board_pin_mux(void)
268 enable_uart3_pin_mux();
269 configure_module_pin_mux(nand_pin_mux
);
270 configure_module_pin_mux(ethernet_pin_mux
);
271 configure_module_pin_mux(gpios_pin_mux
);
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