2 * Board functions for TI AM335X based rut board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * u-boot:/board/ti/am335x/board.c
9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/omap.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
35 #include "../common/factoryset.h"
36 #include "../../../drivers/video/da8xx-fb.h"
38 DECLARE_GLOBAL_DATA_PTR
;
41 * Read header information from EEPROM into global structure.
43 static int read_eeprom(void)
48 #ifdef CONFIG_SPL_BUILD
49 static void board_init_ddr(void)
51 struct emif_regs rut_ddr3_emif_reg_data
= {
52 .sdram_config
= 0x61C04AB2,
53 .sdram_tim1
= 0x0888A39B,
54 .sdram_tim2
= 0x26337FDA,
55 .sdram_tim3
= 0x501F830F,
56 .emif_ddr_phy_ctlr_1
= 0x6,
57 .zq_config
= 0x50074BE4,
61 struct ddr_data rut_ddr3_data
= {
62 .datardsratio0
= 0x3b,
63 .datawdsratio0
= 0x85,
64 .datafwsratio0
= 0x100,
65 .datawrsratio0
= 0xc1,
68 struct cmd_control rut_ddr3_cmd_ctrl_data
= {
77 const struct ctrl_ioregs ioregs
= {
78 .cm0ioctl
= RUT_IOCTRL_VAL
,
79 .cm1ioctl
= RUT_IOCTRL_VAL
,
80 .cm2ioctl
= RUT_IOCTRL_VAL
,
81 .dt0ioctl
= RUT_IOCTRL_VAL
,
82 .dt1ioctl
= RUT_IOCTRL_VAL
,
85 config_ddr(DDR_PLL_FREQ
, &ioregs
, &rut_ddr3_data
,
86 &rut_ddr3_cmd_ctrl_data
, &rut_ddr3_emif_reg_data
, 0);
89 static int request_and_pulse_reset(int gpio
, const char *name
)
92 const int delay_us
= 2000; /* 2ms */
94 ret
= gpio_request(gpio
, name
);
96 printf("%s: Unable to request %s\n", __func__
, name
);
100 ret
= gpio_direction_output(gpio
, 0);
102 printf("%s: Unable to set %s as output\n", __func__
, name
);
108 gpio_set_value(gpio
, 1);
118 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
119 #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
120 #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
121 #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
123 #define REQUEST_AND_PULSE_RESET(N) \
124 request_and_pulse_reset(N, #N);
126 static void spl_siemens_board_init(void)
128 REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO
);
129 REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO
);
130 REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO
);
132 #endif /* if def CONFIG_SPL_BUILD */
134 #if defined(CONFIG_DRIVER_TI_CPSW)
135 static void cpsw_control(int enabled
)
137 /* VTP can be added here */
142 static struct cpsw_slave_data cpsw_slaves
[] = {
144 .slave_reg_ofs
= 0x208,
145 .sliver_reg_ofs
= 0xd80,
147 .phy_if
= PHY_INTERFACE_MODE_RMII
,
150 .slave_reg_ofs
= 0x308,
151 .sliver_reg_ofs
= 0xdc0,
153 .phy_if
= PHY_INTERFACE_MODE_RMII
,
157 static struct cpsw_platform_data cpsw_data
= {
158 .mdio_base
= CPSW_MDIO_BASE
,
159 .cpsw_base
= CPSW_BASE
,
162 .cpdma_reg_ofs
= 0x800,
164 .slave_data
= cpsw_slaves
,
165 .ale_reg_ofs
= 0xd00,
167 .host_port_reg_ofs
= 0x108,
168 .hw_stats_reg_ofs
= 0x900,
169 .bd_ram_ofs
= 0x2000,
170 .mac_control
= (1 << 5),
171 .control
= cpsw_control
,
173 .version
= CPSW_CTRL_VERSION_2
,
176 #if defined(CONFIG_DRIVER_TI_CPSW) || \
177 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
178 int board_eth_init(bd_t
*bis
)
180 struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
184 #ifndef CONFIG_SPL_BUILD
185 factoryset_env_set();
188 /* Set rgmii mode and enable rmii clock to be sourced from chip */
189 writel((RMII_MODE_ENABLE
| RMII_CHIPCKL_ENABLE
), &cdev
->miisel
);
191 rv
= cpsw_register(&cpsw_data
);
193 printf("Error %d registering CPSW switch\n", rv
);
198 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
199 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
201 #if defined(CONFIG_HW_WATCHDOG)
202 static bool hw_watchdog_init_done
;
203 static int hw_watchdog_trigger_level
;
205 void hw_watchdog_reset(void)
207 if (!hw_watchdog_init_done
)
210 hw_watchdog_trigger_level
= hw_watchdog_trigger_level
? 0 : 1;
211 gpio_set_value(WATCHDOG_TRIGGER_GPIO
, hw_watchdog_trigger_level
);
214 void hw_watchdog_init(void)
216 gpio_request(WATCHDOG_TRIGGER_GPIO
, "watchdog_trigger");
217 gpio_direction_output(WATCHDOG_TRIGGER_GPIO
, hw_watchdog_trigger_level
);
221 hw_watchdog_init_done
= 1;
223 #endif /* defined(CONFIG_HW_WATCHDOG) */
225 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
226 static struct da8xx_panel lcd_panels
[] = {
227 /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
229 .name
= "KWH043MC17-F01",
232 .hfp
= 50, /* no spec, "don't care" values */
238 .pxl_clk
= 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
241 /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
243 .name
= "KWH043ST20-F01",
246 .hfp
= 50, /* no spec, "don't care" values */
252 .pxl_clk
= 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
255 /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
257 .name
= "MI0430VT-1",
260 .hfp
= 50, /* no spec, "don't care" values */
266 .pxl_clk
= 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
271 static const struct display_panel disp_panels
[] = {
292 static const struct lcd_ctrl_config lcd_cfgs
[] = {
303 .invert_line_clock
= 1,
304 .invert_frm_clock
= 1,
319 .invert_line_clock
= 1,
320 .invert_frm_clock
= 1,
335 .invert_line_clock
= 1,
336 .invert_frm_clock
= 1,
344 /* no console on this board */
345 int board_cfb_skip(void)
350 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
351 #define PLL_GET_N(v) (v & 0x7f)
353 static struct dpll_regs dpll_lcd_regs
= {
354 .cm_clkmode_dpll
= CM_WKUP
+ 0x98,
355 .cm_idlest_dpll
= CM_WKUP
+ 0x48,
356 .cm_clksel_dpll
= CM_WKUP
+ 0x54,
359 static int get_clk(struct dpll_regs
*dpll_regs
)
365 val
= readl(dpll_regs
->cm_clksel_dpll
);
368 f
= (m
* V_OSCK
) / n
;
375 return get_clk(&dpll_lcd_regs
);
378 static int conf_disp_pll(int m
, int n
)
380 struct cm_perpll
*cmper
= (struct cm_perpll
*)CM_PER
;
381 struct dpll_params dpll_lcd
= {m
, n
, -1, -1, -1, -1, -1};
382 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
383 struct cm_wkuppll
*cmwkup
= (struct cm_wkuppll
*)CM_WKUP
;
386 u32
*const clk_domains
[] = {
390 u32
*const clk_modules_explicit_en
[] = {
392 &cmper
->lcdcclkstctrl
,
396 do_enable_clocks(clk_domains
, clk_modules_explicit_en
, 1);
398 do_setup_dpll(&dpll_lcd_regs
, &dpll_lcd
);
400 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
401 writel(0x64, &cmwkup
->resv6
[3]); /* 0x50 */
402 writel(0x800, &cmwkup
->resv6
[2]); /* 0x4c */
403 writel(readl(&cmwkup
->clkmoddplldisp
) | CM_CLKMODE_DPLL_SSC_EN_MASK
,
404 &cmwkup
->clkmoddplldisp
); /* 0x98 */
409 static int set_gpio(int gpio
, int state
)
411 gpio_request(gpio
, "temp");
412 gpio_direction_output(gpio
, state
);
413 gpio_set_value(gpio
, state
);
418 static int enable_lcd(void)
420 unsigned char buf
[1];
422 set_gpio(BOARD_LCD_RESET
, 0);
424 set_gpio(BOARD_LCD_RESET
, 1);
428 kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0
);
432 i2c_write(0x24, 0x7, 1, buf
, 1);
434 i2c_write(0x24, 0x8, 1, buf
, 1);
438 int arch_early_init_r(void)
444 static int board_video_init(void)
447 int anzdisp
= ARRAY_SIZE(lcd_panels
);
450 for (i
= 0; i
< anzdisp
; i
++) {
451 if (strncmp((const char *)factory_dat
.disp_name
,
453 strlen((const char *)factory_dat
.disp_name
)) == 0) {
454 printf("DISPLAY: %s\n", factory_dat
.disp_name
);
460 printf("%s: %s not found, using default %s\n", __func__
,
461 factory_dat
.disp_name
, lcd_panels
[i
].name
);
463 conf_disp_pll(24, 1);
464 da8xx_video_init(&lcd_panels
[display
], &lcd_cfgs
[display
],
465 lcd_cfgs
[display
].bpp
);
469 #endif /* ifdef CONFIG_VIDEO */
471 #ifdef CONFIG_BOARD_LATE_INIT
472 int board_late_init(void)
475 char tmp
[2 * MAX_STRING_LENGTH
+ 2];
477 omap_nand_switch_ecc(1, 8);
479 if (factory_dat
.asn
[0] != 0)
480 sprintf(tmp
, "%s_%s", factory_dat
.asn
,
481 factory_dat
.comp_version
);
483 strcpy(tmp
, "QMX7.E38_4.0");
485 ret
= env_set("boardid", tmp
);
487 printf("error setting board id\n");
493 #include "../common/board.c"