4 * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/ddr_defs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
20 DECLARE_GLOBAL_DATA_PTR
;
22 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
24 #if defined(CONFIG_SPL_BUILD)
26 /* DDR3 RAM timings */
27 static const struct ddr_data ddr3_data
= {
28 .datardsratio0
= MT41K128MJT187E_RD_DQS
,
29 .datawdsratio0
= MT41K128MJT187E_WR_DQS
,
30 .datafwsratio0
= MT41K128MJT187E_PHY_FIFO_WE
,
31 .datawrsratio0
= MT41K128MJT187E_PHY_WR_DATA
,
34 static const struct cmd_control ddr3_cmd_ctrl_data
= {
35 .cmd0csratio
= MT41K128MJT187E_RATIO
,
36 .cmd0iclkout
= MT41K128MJT187E_INVERT_CLKOUT
,
37 .cmd1csratio
= MT41K128MJT187E_RATIO
,
38 .cmd1iclkout
= MT41K128MJT187E_INVERT_CLKOUT
,
39 .cmd2csratio
= MT41K128MJT187E_RATIO
,
40 .cmd2iclkout
= MT41K128MJT187E_INVERT_CLKOUT
,
43 static struct emif_regs ddr3_emif_reg_data
= {
44 .sdram_config
= MT41K128MJT187E_EMIF_SDCFG
,
45 .ref_ctrl
= MT41K128MJT187E_EMIF_SDREF
,
46 .sdram_tim1
= MT41K128MJT187E_EMIF_TIM1
,
47 .sdram_tim2
= MT41K128MJT187E_EMIF_TIM2
,
48 .sdram_tim3
= MT41K128MJT187E_EMIF_TIM3
,
49 .zq_config
= MT41K128MJT187E_ZQ_CFG
,
50 .emif_ddr_phy_ctlr_1
= MT41K128MJT187E_EMIF_READ_LATENCY
|
54 const struct ctrl_ioregs ddr3_ioregs
= {
55 .cm0ioctl
= MT41K128MJT187E_IOCTRL_VALUE
,
56 .cm1ioctl
= MT41K128MJT187E_IOCTRL_VALUE
,
57 .cm2ioctl
= MT41K128MJT187E_IOCTRL_VALUE
,
58 .dt0ioctl
= MT41K128MJT187E_IOCTRL_VALUE
,
59 .dt1ioctl
= MT41K128MJT187E_IOCTRL_VALUE
,
62 #ifdef CONFIG_SPL_OS_BOOT
63 int spl_start_uboot(void)
65 /* break into full u-boot on 'c' */
66 return serial_tstc() && serial_getc() == 'c';
70 #define OSC (V_OSCK/1000000)
71 const struct dpll_params dpll_ddr_266
= {
72 266, OSC
-1, 1, -1, -1, -1, -1};
73 const struct dpll_params dpll_ddr_303
= {
74 303, OSC
-1, 1, -1, -1, -1, -1};
75 const struct dpll_params dpll_ddr_400
= {
76 400, OSC
-1, 1, -1, -1, -1, -1};
78 void am33xx_spl_board_init(void)
81 * The pengwyn board uses the TPS650250 PMIC without I2C
82 * interface and will output the following fixed voltages:
83 * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
84 * VLDO1=1V8 (IO) VLDO2=1V8(IO)
85 * Vcore=1V1 is fixed, generated by TPS62231
88 /* Get the frequency */
89 dpll_mpu_opp100
.m
= am335x_get_efuse_mpu_max_freq(cdev
);
91 /* Set CORE Frequencies to OPP100 */
92 do_setup_dpll(&dpll_core_regs
, &dpll_core_opp100
);
94 /* 720MHz cpu, this might change on newer board revisions */
95 dpll_mpu_opp100
.m
= MPUPLL_M_720
;
96 do_setup_dpll(&dpll_mpu_regs
, &dpll_mpu_opp100
);
99 const struct dpll_params
*get_dpll_ddr_params(void)
101 /* future configs can return other clock settings */
102 return &dpll_ddr_303
;
105 void set_uart_mux_conf(void)
107 enable_uart0_pin_mux();
110 void set_mux_conf_regs(void)
112 enable_board_pin_mux();
115 void sdram_init(void)
117 config_ddr(303, &ddr3_ioregs
, &ddr3_data
,
118 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
120 #endif /* if CONFIG_SPL_BUILD */
123 * Basic board specific setup. Pinmux has been handled already.
127 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
128 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
133 #ifdef CONFIG_DRIVER_TI_CPSW
134 static void cpsw_control(int enabled
)
136 /* VTP can be added here */
140 static struct cpsw_slave_data cpsw_slaves
[] = {
142 .slave_reg_ofs
= 0x208,
143 .sliver_reg_ofs
= 0xd80,
145 .phy_if
= PHY_INTERFACE_MODE_MII
,
149 static struct cpsw_platform_data cpsw_data
= {
150 .mdio_base
= CPSW_MDIO_BASE
,
151 .cpsw_base
= CPSW_BASE
,
154 .cpdma_reg_ofs
= 0x800,
156 .slave_data
= cpsw_slaves
,
157 .ale_reg_ofs
= 0xd00,
159 .host_port_reg_ofs
= 0x108,
160 .hw_stats_reg_ofs
= 0x900,
161 .bd_ram_ofs
= 0x2000,
162 .mac_control
= (1 << 5),
163 .control
= cpsw_control
,
165 .version
= CPSW_CTRL_VERSION_2
,
168 int board_eth_init(bd_t
*bis
)
172 uint32_t mac_hi
, mac_lo
;
174 if (!eth_getenv_enetaddr("ethaddr", mac_addr
)) {
175 printf("<ethaddr> not set. Reading from E-fuse\n");
176 /* try reading mac address from efuse */
177 mac_lo
= readl(&cdev
->macid0l
);
178 mac_hi
= readl(&cdev
->macid0h
);
179 mac_addr
[0] = mac_hi
& 0xFF;
180 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
181 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
182 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
183 mac_addr
[4] = mac_lo
& 0xFF;
184 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
186 if (is_valid_ethaddr(mac_addr
))
187 eth_env_set_enetaddr("ethaddr", mac_addr
);
192 writel(MII_MODE_ENABLE
, &cdev
->miisel
);
194 rv
= cpsw_register(&cpsw_data
);
196 printf("Error %d registering CPSW switch\n", rv
);
201 #endif /* if CONFIG_DRIVER_TI_CPSW */