board/silica/pengwyn/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <env.h>
  10 #include <serial.h>
  11 #include <asm/arch/cpu.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/ddr_defs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <i2c.h>
  17 #include <phy.h>
  18 #include <cpsw.h>
  19 #include "board.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  24
  25 #if defined(CONFIG_SPL_BUILD)
  26
  27 /* DDR3 RAM timings */
  28 static const struct ddr_data ddr3_data = {
  29         .datardsratio0 = MT41K128MJT187E_RD_DQS,
  30         .datawdsratio0 = MT41K128MJT187E_WR_DQS,
  31         .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
  32         .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
  33 };
  34
  35 static const struct cmd_control ddr3_cmd_ctrl_data = {
  36         .cmd0csratio = MT41K128MJT187E_RATIO,
  37         .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  38         .cmd1csratio = MT41K128MJT187E_RATIO,
  39         .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  40         .cmd2csratio = MT41K128MJT187E_RATIO,
  41         .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  42 };
  43
  44 static struct emif_regs ddr3_emif_reg_data = {
  45         .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
  46         .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
  47         .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
  48         .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
  49         .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
  50         .zq_config = MT41K128MJT187E_ZQ_CFG,
  51         .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
  52                                 PHY_EN_DYN_PWRDN,
  53 };
  54
  55 const struct ctrl_ioregs ddr3_ioregs = {
  56         .cm0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  57         .cm1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  58         .cm2ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  59         .dt0ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  60         .dt1ioctl               = MT41K128MJT187E_IOCTRL_VALUE,
  61 };
  62
  63 #ifdef CONFIG_SPL_OS_BOOT
  64 int spl_start_uboot(void)
  65 {
  66         /* break into full u-boot on 'c' */
  67         return serial_tstc() && serial_getc() == 'c';
  68 }
  69 #endif
  70
  71 #define OSC     (V_OSCK/1000000)
  72 const struct dpll_params dpll_ddr_266 = {
  73                 266, OSC-1, 1, -1, -1, -1, -1};
  74 const struct dpll_params dpll_ddr_303 = {
  75                 303, OSC-1, 1, -1, -1, -1, -1};
  76 const struct dpll_params dpll_ddr_400 = {
  77                 400, OSC-1, 1, -1, -1, -1, -1};
  78
  79 void am33xx_spl_board_init(void)
  80 {
  81         /*
  82          * The pengwyn board uses the TPS650250 PMIC  without I2C
  83          * interface and will output the following fixed voltages:
  84          * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
  85          * VLDO1=1V8 (IO) VLDO2=1V8(IO)
  86          * Vcore=1V1 is fixed, generated by TPS62231
  87          */
  88
  89         /* Get the frequency */
  90         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  91
  92         /* Set CORE Frequencies to OPP100 */
  93         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  94
  95         /* 720MHz cpu, this might change on newer board revisions */
  96         dpll_mpu_opp100.m = MPUPLL_M_720;
  97         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  98 }
  99
 100 const struct dpll_params *get_dpll_ddr_params(void)
 101 {
 102         /* future configs can return other clock settings */
 103         return &dpll_ddr_303;
 104 }
 105
 106 void set_uart_mux_conf(void)
 107 {
 108         enable_uart0_pin_mux();
 109 }
 110
 111 void set_mux_conf_regs(void)
 112 {
 113         enable_board_pin_mux();
 114 }
 115
 116 void sdram_init(void)
 117 {
 118         config_ddr(303, &ddr3_ioregs, &ddr3_data,
 119                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 120 }
 121 #endif /* if CONFIG_SPL_BUILD */
 122
 123 /*
 124  * Basic board specific setup.  Pinmux has been handled already.
 125  */
 126 int board_init(void)
 127 {
 128         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 129         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 130         gpmc_init();
 131         return 0;
 132 }
 133
 134 #ifdef CONFIG_DRIVER_TI_CPSW
 135 static void cpsw_control(int enabled)
 136 {
 137         /* VTP can be added here */
 138         return;
 139 }
 140
 141 static struct cpsw_slave_data cpsw_slaves[] = {
 142         {
 143                 .slave_reg_ofs  = 0x208,
 144                 .sliver_reg_ofs = 0xd80,
 145                 .phy_addr       = 1,
 146                 .phy_if         = PHY_INTERFACE_MODE_MII,
 147         },
 148 };
 149
 150 static struct cpsw_platform_data cpsw_data = {
 151         .mdio_base              = CPSW_MDIO_BASE,
 152         .cpsw_base              = CPSW_BASE,
 153         .mdio_div               = 0xff,
 154         .channels               = 8,
 155         .cpdma_reg_ofs          = 0x800,
 156         .slaves                 = 1,
 157         .slave_data             = cpsw_slaves,
 158         .ale_reg_ofs            = 0xd00,
 159         .ale_entries            = 1024,
 160         .host_port_reg_ofs      = 0x108,
 161         .hw_stats_reg_ofs       = 0x900,
 162         .bd_ram_ofs             = 0x2000,
 163         .mac_control            = (1 << 5),
 164         .control                = cpsw_control,
 165         .host_port_num          = 0,
 166         .version                = CPSW_CTRL_VERSION_2,
 167 };
 168
 169 int board_eth_init(bd_t *bis)
 170 {
 171         int rv, n = 0;
 172         uint8_t mac_addr[6];
 173         uint32_t mac_hi, mac_lo;
 174
 175         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 176                 printf("<ethaddr> not set. Reading from E-fuse\n");
 177                 /* try reading mac address from efuse */
 178                 mac_lo = readl(&cdev->macid0l);
 179                 mac_hi = readl(&cdev->macid0h);
 180                 mac_addr[0] = mac_hi & 0xFF;
 181                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 182                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 183                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 184                 mac_addr[4] = mac_lo & 0xFF;
 185                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 186
 187                 if (is_valid_ethaddr(mac_addr))
 188                         eth_env_set_enetaddr("ethaddr", mac_addr);
 189                 else
 190                         return n;
 191         }
 192
 193         writel(MII_MODE_ENABLE, &cdev->miisel);
 194
 195         rv = cpsw_register(&cpsw_data);
 196         if (rv < 0)
 197                 printf("Error %d registering CPSW switch\n", rv);
 198         else
 199                 n += rv;
 200         return n;
 201 }
 202 #endif /* if CONFIG_DRIVER_TI_CPSW */