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git.ipfire.org Git - thirdparty/u-boot.git/blob - board/spc1920/spc1920.c
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
7 * SPDX-License-Identifier: GPL-2.0+
16 #define _NOT_USED_ 0xFFFFFFFF
18 static long int dram_size (long int, long int *, long int);
20 const uint sdram_table
[] = {
22 * Single Read. (Offset 0 in UPMB RAM)
24 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
25 0x1FF77C47, /* last */
27 * SDRAM Initialization (offset 5 in UPMB RAM)
29 * This is no UPM entry point. The following definition uses
30 * the remaining space to establish an initialization
31 * sequence, which is executed by a RUN command.
34 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
36 * Burst Read. (Offset 8 in UPMB RAM)
38 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
39 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
40 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
41 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
43 * Single Write. (Offset 18 in UPMB RAM)
45 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
46 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
48 * Burst Write. (Offset 20 in UPMB RAM)
50 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
51 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
53 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
54 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
56 * Refresh (Offset 30 in UPMB RAM)
58 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
59 0xFFFFFC84, 0xFFFFFC07, /* last */
60 _NOT_USED_
, _NOT_USED_
,
61 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
63 * Exception. (Offset 3c in UPMB RAM)
65 0x7FFFFC07, /* last */
66 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
69 phys_size_t
initdram (int board_type
)
71 volatile immap_t
*immr
= (immap_t
*) CONFIG_SYS_IMMR
;
72 volatile memctl8xx_t
*memctl
= &immr
->im_memctl
;
73 /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */
76 long int size8
, size9
;
80 * Configure UPMB for SDRAM
82 upmconfig (UPMB
, (uint
*)sdram_table
, sizeof(sdram_table
)/sizeof(uint
));
86 memctl
->memc_mptpr
= CONFIG_SYS_MPTPR
;
88 /* burst length=4, burst type=sequential, CAS latency=2 */
89 memctl
->memc_mar
= CONFIG_SYS_MAR
;
92 * Map controller bank 1 to the SDRAM bank at preliminary address.
94 memctl
->memc_or1
= CONFIG_SYS_OR1_PRELIM
;
95 memctl
->memc_br1
= CONFIG_SYS_BR1_PRELIM
;
97 /* initialize memory address register */
98 memctl
->memc_mbmr
= CONFIG_SYS_MBMR_8COL
; /* refresh not enabled yet */
100 /* mode initialization (offset 5) */
101 udelay (200); /* 0x80006105 */
102 memctl
->memc_mcr
= MCR_OP_RUN
| MCR_UPM_B
| MCR_MB_CS1
| MCR_MLCF (1) | MCR_MAD (0x05);
104 /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
105 udelay (1); /* 0x80006130 */
106 memctl
->memc_mcr
= MCR_OP_RUN
| MCR_UPM_B
| MCR_MB_CS1
| MCR_MLCF (1) | MCR_MAD (0x30);
107 udelay (1); /* 0x80006130 */
108 memctl
->memc_mcr
= MCR_OP_RUN
| MCR_UPM_B
| MCR_MB_CS1
| MCR_MLCF (1) | MCR_MAD (0x30);
109 udelay (1); /* 0x80006106 */
110 memctl
->memc_mcr
= MCR_OP_RUN
| MCR_UPM_B
| MCR_MB_CS1
| MCR_MLCF (1) | MCR_MAD (0x06);
112 memctl
->memc_mbmr
|= MBMR_PTBE
; /* refresh enabled */
116 /* Need at least 10 DRAM accesses to stabilize */
117 for (i
= 0; i
< 10; ++i
) {
118 volatile unsigned long *addr
=
119 (volatile unsigned long *) CONFIG_SYS_SDRAM_BASE
;
127 * Check Bank 0 Memory Size for re-configuration
131 size8
= dram_size (CONFIG_SYS_MBMR_8COL
, (long *)CONFIG_SYS_SDRAM_BASE
, SDRAM_MAX_SIZE
);
138 size9
= dram_size (CONFIG_SYS_MBMR_9COL
, (long *)CONFIG_SYS_SDRAM_BASE
, SDRAM_MAX_SIZE
);
140 if (size8
< size9
) { /* leave configuration at 9 columns */
142 memctl
->memc_mbmr
= CONFIG_SYS_MBMR_9COL
| MBMR_PTBE
;
144 } else { /* back to 8 columns */
146 memctl
->memc_mbmr
= CONFIG_SYS_MBMR_8COL
| MBMR_PTBE
;
154 memctl
->memc_or1
= ((-size_b0
) & 0xFFFF0000) |
155 OR_CSNT_SAM
| OR_G5LS
| SDRAM_TIMING
;
156 memctl
->memc_br1
= (CONFIG_SYS_SDRAM_BASE
& BR_BA_MSK
) | BR_MS_UPMB
| BR_V
;
159 /* initalize the DSP Host Port Interface */
163 memctl
->memc_or4
= CONFIG_SYS_OR4
;
164 memctl
->memc_br4
= CONFIG_SYS_BR4
;
171 * Check memory range for valid RAM. A simple memory test determines
172 * the actually available RAM size between addresses `base' and
173 * `base + maxsize'. Some (not all) hardware errors are detected:
174 * - short between address lines
175 * - short between data lines
177 static long int dram_size (long int mbmr_value
, long int *base
,
180 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
181 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
183 memctl
->memc_mbmr
= mbmr_value
;
185 return (get_ram_size (base
, maxsize
));
189 /************* other stuff ******************/
192 int board_early_init_f(void)
194 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
196 /* Set Go/NoGo led (PA15) to color red */
197 immap
->im_ioport
.iop_papar
&= ~0x1;
198 immap
->im_ioport
.iop_paodr
&= ~0x1;
199 immap
->im_ioport
.iop_padir
|= 0x1;
200 immap
->im_ioport
.iop_padat
|= 0x1;
203 /* Turn on LED PD9 */
204 immap
->im_ioport
.iop_pdpar
&= ~(0x0040);
205 immap
->im_ioport
.iop_pddir
|= 0x0040;
206 immap
->im_ioport
.iop_pddat
|= 0x0040;
210 * Enable console on SMC1. This requires turning on
211 * the com2_en signal and SMC1_DISABLE
214 /* SMC1_DISABLE: PB17 */
215 immap
->im_cpm
.cp_pbodr
&= ~0x4000;
216 immap
->im_cpm
.cp_pbpar
&= ~0x4000;
217 immap
->im_cpm
.cp_pbdir
|= 0x4000;
218 immap
->im_cpm
.cp_pbdat
&= ~0x4000;
221 immap
->im_ioport
.iop_pdpar
&= ~0x0020;
222 immap
->im_ioport
.iop_pddir
&= ~0x4000;
223 immap
->im_ioport
.iop_pddir
|= 0x0020;
224 immap
->im_ioport
.iop_pddat
|= 0x0020;
227 #ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
228 immap
->im_cpm
.cp_simode
|= 0x7000;
229 immap
->im_cpm
.cp_simode
&= ~(0x8000);
235 int last_stage_init(void)
237 #ifdef CONFIG_SPC1920_HPI_TEST
238 printf("CMB1920 Host Port Interface Test: %s\n",
239 hpi_test() ? "Failed!" : "OK");
244 int checkboard (void)
246 puts("Board: SPC1920\n");