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git.ipfire.org Git - people/ms/u-boot.git/blob - board/spd8xx/spd8xx.c
6387f8a65c50aa98dee5bfbe398cef2e7c8654af
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* ------------------------------------------------------------------------- */
31 static long int dram_size (long int, long int *, long int);
33 /* ------------------------------------------------------------------------- */
35 #define _NOT_USED_ 0xFFFFFFFF
37 const uint sharc_table
[] = {
39 * Single Read. (Offset 0 in UPM RAM)
41 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
42 0xFFFFEC05, /* last */
43 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
45 * Burst Read. (Offset 8 in UPM RAM)
48 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
49 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
50 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
51 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
53 * Single Write. (Offset 18 in UPM RAM)
55 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
56 0xFFFFEC05, /* last */
57 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
59 * Burst Write. (Offset 20 in UPM RAM)
62 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
63 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
64 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
65 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
67 * Refresh (Offset 30 in UPM RAM)
70 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
71 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
72 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
74 * Exception. (Offset 3c in UPM RAM)
76 0x7FFFFC07, /* last */
77 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
81 const uint sdram_table
[] = {
83 * Single Read. (Offset 0 in UPM RAM)
85 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
86 0x1FF77C47, /* last */
88 * SDRAM Initialization (offset 5 in UPM RAM)
90 * This is no UPM entry point. The following definition uses
91 * the remaining space to establish an initialization
92 * sequence, which is executed by a RUN command.
95 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
97 * Burst Read. (Offset 8 in UPM RAM)
99 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
100 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
101 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
102 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
104 * Single Write. (Offset 18 in UPM RAM)
106 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
107 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
109 * Burst Write. (Offset 20 in UPM RAM)
111 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
112 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
114 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
115 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
117 * Refresh (Offset 30 in UPM RAM)
119 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
120 0xFFFFFC84, 0xFFFFFC07, /* last */
121 _NOT_USED_
, _NOT_USED_
,
122 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
124 * Exception. (Offset 3c in UPM RAM)
126 0x7FFFFC07, /* last */
127 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
130 /* ------------------------------------------------------------------------- */
134 * Check Board Identity:
138 int checkboard (void)
140 puts ("Board: SPD823TS\n");
144 /* ------------------------------------------------------------------------- */
146 phys_size_t
initdram (int board_type
)
148 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
149 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
154 * Map controller bank 2 to the SRAM bank at preliminary address.
156 memctl
->memc_or2
= CFG_OR2
;
157 memctl
->memc_br2
= CFG_BR2
;
161 * Map controller bank 4 to the PER8 bank.
163 memctl
->memc_or4
= CFG_OR4
;
164 memctl
->memc_br4
= CFG_BR4
;
167 /* Configure SHARC at UMA */
168 upmconfig (UPMA
, (uint
*) sharc_table
,
169 sizeof (sharc_table
) / sizeof (uint
));
170 /* Map controller bank 5 to the SHARC */
171 memctl
->memc_or5
= CFG_OR5
;
172 memctl
->memc_br5
= CFG_BR5
;
175 memctl
->memc_mamr
= 0x00001000;
177 /* Configure SDRAM at UMB */
178 upmconfig (UPMB
, (uint
*) sdram_table
,
179 sizeof (sdram_table
) / sizeof (uint
));
181 memctl
->memc_mptpr
= CFG_MPTPR_1BK_8K
;
183 memctl
->memc_mar
= 0x00000088;
186 * Map controller bank 3 to the SDRAM bank at preliminary address.
188 memctl
->memc_or3
= CFG_OR3_PRELIM
;
189 memctl
->memc_br3
= CFG_BR3_PRELIM
;
191 memctl
->memc_mbmr
= CFG_MBMR_8COL
; /* refresh not enabled yet */
194 memctl
->memc_mcr
= 0x80806105;
196 memctl
->memc_mcr
= 0x80806130;
198 memctl
->memc_mcr
= 0x80806130;
200 memctl
->memc_mcr
= 0x80806106;
202 memctl
->memc_mbmr
|= MBMR_PTBE
; /* refresh enabled */
205 * Check Bank 0 Memory Size for re-configuration
208 dram_size (CFG_MBMR_8COL
, SDRAM_BASE3_PRELIM
,
211 memctl
->memc_mbmr
= CFG_MBMR_8COL
| MBMR_PTBE
;
216 /* ------------------------------------------------------------------------- */
219 * Check memory range for valid RAM. A simple memory test determines
220 * the actually available RAM size between addresses `base' and
221 * `base + maxsize'. Some (not all) hardware errors are detected:
222 * - short between address lines
223 * - short between data lines
226 static long int dram_size (long int mamr_value
, long int *base
,
229 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
230 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
232 memctl
->memc_mbmr
= mamr_value
;
234 return (get_ram_size (base
, maxsize
));
237 /* ------------------------------------------------------------------------- */
239 void reset_phy (void)
241 immap_t
*immr
= (immap_t
*) CFG_IMMR
;
244 /* Configure extra port pins for NS DP83843 PHY */
245 immr
->im_ioport
.iop_papar
&= ~(PA_ENET_MDC
| PA_ENET_MDIO
);
247 sreg
= immr
->im_ioport
.iop_padir
;
248 sreg
|= PA_ENET_MDC
; /* Mgmt. Data Clock is Output */
249 sreg
&= ~(PA_ENET_MDIO
); /* Mgmt. Data I/O is bidirect. => Input */
250 immr
->im_ioport
.iop_padir
= sreg
;
252 immr
->im_ioport
.iop_padat
&= ~(PA_ENET_MDC
); /* set MDC = 0 */
255 * RESET in implemented by a positive pulse of at least 1 us
258 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
260 * Note: The RESET pin is high active, but there is an
261 * inverter on the SPD823TS board...
263 immr
->im_ioport
.iop_pcpar
&= ~(PC_ENET_RESET
);
264 immr
->im_ioport
.iop_pcdir
|= PC_ENET_RESET
;
265 /* assert RESET signal of PHY */
266 immr
->im_ioport
.iop_pcdat
&= ~(PC_ENET_RESET
);
268 /* de-assert RESET signal of PHY */
269 immr
->im_ioport
.iop_pcdat
|= PC_ENET_RESET
;
273 /* ------------------------------------------------------------------------- */
275 void ide_set_reset (int on
)
277 volatile immap_t
*immr
= (immap_t
*) CFG_IMMR
;
280 * Configure PC for IDE Reset Pin
282 if (on
) { /* assert RESET */
283 immr
->im_ioport
.iop_pcdat
&= ~(CFG_PC_IDE_RESET
);
284 } else { /* release RESET */
285 immr
->im_ioport
.iop_pcdat
|= CFG_PC_IDE_RESET
;
288 /* program port pin as GPIO output */
289 immr
->im_ioport
.iop_pcpar
&= ~(CFG_PC_IDE_RESET
);
290 immr
->im_ioport
.iop_pcso
&= ~(CFG_PC_IDE_RESET
);
291 immr
->im_ioport
.iop_pcdir
|= CFG_PC_IDE_RESET
;
294 /* ------------------------------------------------------------------------- */