board/spear/common/spr_lowlevel_init.S

   1 /*
   2  * (C) Copyright 2006
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9
  10 /*
  11  * platform specific initializations are already done in Xloader
  12  * Initializations already done include
  13  * DDR, PLLs, IP's clock enable and reset release etc
  14  */
  15 .globl lowlevel_init
  16 lowlevel_init:
  17         mov     pc, lr
  18
  19 /* void setfreq(unsigned int device, unsigned int frequency) */
  20 .global setfreq
  21 setfreq:
  22         stmfd   sp!,{r14}
  23         stmfd   sp!,{r0-r12}
  24
  25         mov     r8,sp
  26         ldr     sp,SRAM_STACK_V
  27
  28         /* Saving the function arguements for later use */
  29         mov     r4,r0
  30         mov     r5,r1
  31
  32         /* Putting DDR into self refresh */
  33         ldr     r0,DDR_07_V
  34         ldr     r1,[r0]
  35         ldr     r2,DDR_ACTIVE_V
  36         bic     r1, r1, r2
  37         str     r1,[r0]
  38         ldr     r0,DDR_57_V
  39         ldr     r1,[r0]
  40         ldr     r2,CYCLES_MASK_V
  41         bic     r1, r1, r2
  42         ldr     r2,REFRESH_CYCLES_V
  43         orr     r1, r1, r2, lsl #16
  44         str     r1,[r0]
  45         ldr     r0,DDR_07_V
  46         ldr     r1,[r0]
  47         ldr     r2,SREFRESH_MASK_V
  48         orr     r1, r1, r2
  49         str     r1,[r0]
  50
  51         /* flush pipeline */
  52         b       flush
  53         .align 5
  54 flush:
  55         /* Delay to ensure self refresh mode */
  56         ldr     r0,SREFRESH_DELAY_V
  57 delay:
  58         sub     r0,r0,#1
  59         cmp     r0,#0
  60         bne     delay
  61
  62         /* Putting system in slow mode */
  63         ldr     r0,SCCTRL_V
  64         mov     r1,#2
  65         str     r1,[r0]
  66
  67         /* Changing PLL(1/2) frequency */
  68         mov     r0,r4
  69         mov     r1,r5
  70
  71         cmp     r4,#0
  72         beq     pll1_freq
  73
  74         /* Change PLL2 (DDR frequency) */
  75         ldr     r6,PLL2_FREQ_V
  76         ldr     r7,PLL2_CNTL_V
  77         b       pll2_freq
  78
  79 pll1_freq:
  80         /* Change PLL1 (CPU frequency) */
  81         ldr     r6,PLL1_FREQ_V
  82         ldr     r7,PLL1_CNTL_V
  83
  84 pll2_freq:
  85         mov     r0,r6
  86         ldr     r1,[r0]
  87         ldr     r2,PLLFREQ_MASK_V
  88         bic     r1,r1,r2
  89         mov     r2,r5,lsr#1
  90         orr     r1,r1,r2,lsl#24
  91         str     r1,[r0]
  92
  93         mov     r0,r7
  94         ldr     r1,P1C0A_V
  95         str     r1,[r0]
  96         ldr     r1,P1C0E_V
  97         str     r1,[r0]
  98         ldr     r1,P1C06_V
  99         str     r1,[r0]
 100         ldr     r1,P1C0E_V
 101         str     r1,[r0]
 102
 103 lock:
 104         ldr     r1,[r0]
 105         and     r1,r1,#1
 106         cmp     r1,#0
 107         beq     lock
 108
 109         /* Putting system back to normal mode */
 110         ldr     r0,SCCTRL_V
 111         mov     r1,#4
 112         str     r1,[r0]
 113
 114         /* Putting DDR back to normal */
 115         ldr     r0,DDR_07_V
 116         ldr     r1,[R0]
 117         ldr     r2,SREFRESH_MASK_V
 118         bic     r1, r1, r2
 119         str     r1,[r0]
 120         ldr     r2,DDR_ACTIVE_V
 121         orr     r1, r1, r2
 122         str     r1,[r0]
 123
 124         /* Delay to ensure self refresh mode */
 125         ldr     r0,SREFRESH_DELAY_V
 126 1:
 127         sub     r0,r0,#1
 128         cmp     r0,#0
 129         bne     1b
 130
 131         mov     sp,r8
 132         /* Resuming back to code */
 133         ldmia   sp!,{r0-r12}
 134         ldmia   sp!,{pc}
 135
 136 SCCTRL_V:
 137         .word 0xfca00000
 138 PLL1_FREQ_V:
 139         .word 0xfca8000C
 140 PLL1_CNTL_V:
 141         .word 0xfca80008
 142 PLL2_FREQ_V:
 143         .word 0xfca80018
 144 PLL2_CNTL_V:
 145         .word 0xfca80014
 146 PLLFREQ_MASK_V:
 147         .word 0xff000000
 148 P1C0A_V:
 149         .word 0x1C0A
 150 P1C0E_V:
 151         .word 0x1C0E
 152 P1C06_V:
 153         .word 0x1C06
 154
 155 SREFRESH_DELAY_V:
 156         .word 0x9999
 157 SRAM_STACK_V:
 158         .word 0xD2800600
 159 DDR_07_V:
 160         .word 0xfc60001c
 161 DDR_ACTIVE_V:
 162         .word 0x01000000
 163 DDR_57_V:
 164         .word 0xfc6000e4
 165 CYCLES_MASK_V:
 166         .word 0xffff0000
 167 REFRESH_CYCLES_V:
 168         .word 0xf0f0
 169 SREFRESH_MASK_V:
 170         .word 0x00010000
 171
 172 .global setfreq_sz
 173 setfreq_sz:
 174         .word setfreq_sz - setfreq