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spl: stm32f7: configure for xip booting
[thirdparty/u-boot.git] / board / st / stm32f746-disco / stm32f746-disco.c
1 /*
2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <ram.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #include <asm/armv7m.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/fmc.h>
17 #include <dm/platform_data/serial_stm32x7.h>
18 #include <asm/arch/stm32_periph.h>
19 #include <asm/arch/stm32_defs.h>
20 #include <asm/arch/syscfg.h>
21 #include <asm/gpio.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
26 {
27 int mr_node;
28
29 mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
30 if (mr_node < 0)
31 return mr_node;
32 *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
33 "reg", 0, mr_size, false);
34 debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
35
36 return 0;
37 }
38 int dram_init(void)
39 {
40 int rv;
41 fdt_addr_t mr_base, mr_size;
42
43 #ifndef CONFIG_SUPPORT_SPL
44 struct udevice *dev;
45 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
46 if (rv) {
47 debug("DRAM init failed: %d\n", rv);
48 return rv;
49 }
50
51 #endif
52 rv = get_memory_base_size(&mr_base, &mr_size);
53 if (rv)
54 return rv;
55 gd->ram_size = mr_size;
56 gd->ram_top = mr_base;
57
58 return rv;
59 }
60
61 int dram_init_banksize(void)
62 {
63 fdt_addr_t mr_base, mr_size;
64 get_memory_base_size(&mr_base, &mr_size);
65 /*
66 * Fill in global info with description of SRAM configuration
67 */
68 gd->bd->bi_dram[0].start = mr_base;
69 gd->bd->bi_dram[0].size = mr_size;
70
71 return 0;
72 }
73
74 #ifdef CONFIG_ETH_DESIGNWARE
75 static int stmmac_setup(void)
76 {
77 clock_setup(SYSCFG_CLOCK_CFG);
78 /* Set >RMII mode */
79 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
80 clock_setup(STMMAC_CLOCK_CFG);
81
82 return 0;
83 }
84
85 int board_early_init_f(void)
86 {
87 stmmac_setup();
88
89 return 0;
90 }
91 #endif
92
93 #ifdef CONFIG_SPL_BUILD
94 #ifdef CONFIG_SPL_OS_BOOT
95 int spl_start_uboot(void)
96 {
97 debug("SPL: booting kernel\n");
98 /* break into full u-boot on 'c' */
99 return serial_tstc() && serial_getc() == 'c';
100 }
101 #endif
102
103 int spl_dram_init(void)
104 {
105 struct udevice *dev;
106 int rv;
107 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
108 if (rv)
109 debug("DRAM init failed: %d\n", rv);
110 return rv;
111 }
112 void spl_board_init(void)
113 {
114 spl_dram_init();
115 preloader_console_init();
116 arch_cpu_init(); /* to configure mpu for sdram rw permissions */
117 }
118 u32 spl_boot_device(void)
119 {
120 return BOOT_DEVICE_XIP;
121 }
122
123 #endif
124 u32 get_board_rev(void)
125 {
126 return 0;
127 }
128
129 int board_late_init(void)
130 {
131 struct gpio_desc gpio = {};
132 int node;
133
134 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
135 if (node < 0)
136 return -1;
137
138 gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
139 GPIOD_IS_OUT);
140
141 if (dm_gpio_is_valid(&gpio)) {
142 dm_gpio_set_value(&gpio, 0);
143 mdelay(10);
144 dm_gpio_set_value(&gpio, 1);
145 }
146
147 /* read button 1*/
148 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
149 if (node < 0)
150 return -1;
151
152 gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
153 &gpio, GPIOD_IS_IN);
154
155 if (dm_gpio_is_valid(&gpio)) {
156 if (dm_gpio_get_value(&gpio))
157 puts("usr button is at HIGH LEVEL\n");
158 else
159 puts("usr button is at LOW LEVEL\n");
160 }
161
162 return 0;
163 }
164
165 int board_init(void)
166 {
167 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
168 return 0;
169 }