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1 if ARCH_SUNXI
2
3 choice
4 prompt "Sunxi SoC Variant"
5
6 config MACH_SUN4I
7 bool "sun4i (Allwinner A10)"
8 select CPU_V7
9 select SUPPORT_SPL
10
11 config MACH_SUN5I
12 bool "sun5i (Allwinner A13)"
13 select CPU_V7
14 select SUPPORT_SPL
15
16 config MACH_SUN6I
17 bool "sun6i (Allwinner A31)"
18 select CPU_V7
19 select SUPPORT_SPL
20
21 config MACH_SUN7I
22 bool "sun7i (Allwinner A20)"
23 select CPU_V7
24 select CPU_V7_HAS_NONSEC
25 select CPU_V7_HAS_VIRT
26 select SUPPORT_SPL
27 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
28
29 config MACH_SUN8I
30 bool "sun8i (Allwinner A23)"
31 select CPU_V7
32 select SUPPORT_SPL
33
34 endchoice
35
36 config DRAM_CLK
37 int "sunxi dram clock speed"
38 default 312 if MACH_SUN6I || MACH_SUN8I
39 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
40 ---help---
41 Set the dram clock speed, valid range 240 - 480, must be a multiple
42 of 24.
43
44 if MACH_SUN5I || MACH_SUN7I
45 config DRAM_MBUS_CLK
46 int "sunxi mbus clock speed"
47 default 300
48 ---help---
49 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
50
51 endif
52
53 config DRAM_ZQ
54 int "sunxi dram zq value"
55 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
56 default 127 if MACH_SUN7I
57 ---help---
58 Set the dram zq value.
59
60 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
61 config DRAM_EMR1
62 int "sunxi dram emr1 value"
63 default 0 if MACH_SUN4I
64 default 4 if MACH_SUN5I || MACH_SUN7I
65 ---help---
66 Set the dram controller emr1 value.
67
68 config DRAM_ODT_EN
69 int "sunxi dram odt_en value"
70 default 0
71 ---help---
72 Set the dram controller odt_en parameter. This can be used to
73 enable/disable the ODT feature.
74
75 config DRAM_TPR3
76 hex "sunxi dram tpr3 value"
77 default 0
78 ---help---
79 Set the dram controller tpr3 parameter. This parameter configures
80 the delay on the command lane and also phase shifts, which are
81 applied for sampling incoming read data. The default value 0
82 means that no phase/delay adjustments are necessary. Properly
83 configuring this parameter increases reliability at high DRAM
84 clock speeds.
85
86 config DRAM_DQS_GATING_DELAY
87 hex "sunxi dram dqs_gating_delay value"
88 default 0
89 ---help---
90 Set the dram controller dqs_gating_delay parmeter. Each byte
91 encodes the DQS gating delay for each byte lane. The delay
92 granularity is 1/4 cycle. For example, the value 0x05060606
93 means that the delay is 5 quarter-cycles for one lane (1.25
94 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
95 The default value 0 means autodetection. The results of hardware
96 autodetection are not very reliable and depend on the chip
97 temperature (sometimes producing different results on cold start
98 and warm reboot). But the accuracy of hardware autodetection
99 is usually good enough, unless running at really high DRAM
100 clocks speeds (up to 600MHz). If unsure, keep as 0.
101
102 choice
103 prompt "sunxi dram timings"
104 default DRAM_TIMINGS_VENDOR_MAGIC
105 ---help---
106 Select the timings of the DDR3 chips.
107
108 config DRAM_TIMINGS_VENDOR_MAGIC
109 bool "Magic vendor timings from Android"
110 ---help---
111 The same DRAM timings as in the Allwinner boot0 bootloader.
112
113 config DRAM_TIMINGS_DDR3_1066F_1333H
114 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
115 ---help---
116 Use the timings of the standard JEDEC DDR3-1066F speed bin for
117 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
118 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
119 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
120 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
121 that down binning to DDR3-1066F is supported (because DDR3-1066F
122 uses a bit faster timings than DDR3-1333H).
123
124 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
125 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
126 ---help---
127 Use the timings of the slowest possible JEDEC speed bin for the
128 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
129 DDR3-800E, DDR3-1066G or DDR3-1333J.
130
131 endchoice
132
133 endif
134
135 config SYS_CONFIG_NAME
136 default "sun4i" if MACH_SUN4I
137 default "sun5i" if MACH_SUN5I
138 default "sun6i" if MACH_SUN6I
139 default "sun7i" if MACH_SUN7I
140 default "sun8i" if MACH_SUN8I
141
142 config SYS_BOARD
143 default "sunxi"
144
145 config SYS_SOC
146 default "sunxi"
147
148 config SPL_FEL
149 bool "SPL/FEL mode support"
150 depends on SPL
151 default n
152
153 config UART0_PORT_F
154 bool "UART0 on MicroSD breakout board"
155 depends on SPL_FEL
156 default n
157 ---help---
158 Repurpose the SD card slot for getting access to the UART0 serial
159 console. Primarily useful only for low level u-boot debugging on
160 tablets, where normal UART0 is difficult to access and requires
161 device disassembly and/or soldering. As the SD card can't be used
162 at the same time, the system can be only booted in the FEL mode.
163 Only enable this if you really know what you are doing.
164
165 config FDTFILE
166 string "Default fdtfile env setting for this board"
167
168 config OLD_SUNXI_KERNEL_COMPAT
169 boolean "Enable workarounds for booting old kernels"
170 default n
171 ---help---
172 Set this to enable various workarounds for old kernels, this results in
173 sub-optimal settings for newer kernels, only enable if needed.
174
175 config MMC0_CD_PIN
176 string "Card detect pin for mmc0"
177 default ""
178 ---help---
179 Set the card detect pin for mmc0, leave empty to not use cd. This
180 takes a string in the format understood by sunxi_name_to_gpio, e.g.
181 PH1 for pin 1 of port H.
182
183 config MMC1_CD_PIN
184 string "Card detect pin for mmc1"
185 default ""
186 ---help---
187 See MMC0_CD_PIN help text.
188
189 config MMC2_CD_PIN
190 string "Card detect pin for mmc2"
191 default ""
192 ---help---
193 See MMC0_CD_PIN help text.
194
195 config MMC3_CD_PIN
196 string "Card detect pin for mmc3"
197 default ""
198 ---help---
199 See MMC0_CD_PIN help text.
200
201 config MMC_SUNXI_SLOT_EXTRA
202 int "mmc extra slot number"
203 default -1
204 ---help---
205 sunxi builds always enable mmc0, some boards also have a second sdcard
206 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
207 support for this.
208
209 config USB0_VBUS_PIN
210 string "Vbus enable pin for usb0 (otg)"
211 default ""
212 ---help---
213 Set the Vbus enable pin for usb0 (otg). This takes a string in the
214 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
215
216 config USB1_VBUS_PIN
217 string "Vbus enable pin for usb1 (ehci0)"
218 default "PH6" if MACH_SUN4I || MACH_SUN7I
219 default "PH27" if MACH_SUN6I
220 ---help---
221 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
222 a string in the format understood by sunxi_name_to_gpio, e.g.
223 PH1 for pin 1 of port H.
224
225 config USB2_VBUS_PIN
226 string "Vbus enable pin for usb2 (ehci1)"
227 default "PH3" if MACH_SUN4I || MACH_SUN7I
228 default "PH24" if MACH_SUN6I
229 ---help---
230 See USB1_VBUS_PIN help text.
231
232 config VIDEO
233 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
234 default y
235 ---help---
236 Say Y here to add support for using a cfb console on the HDMI, LCD
237 or VGA output found on most sunxi devices. See doc/README.video for
238 info on how to select the video output and mode.
239
240 config VIDEO_HDMI
241 boolean "HDMI output support"
242 depends on VIDEO && !MACH_SUN8I
243 default y
244 ---help---
245 Say Y here to add support for outputting video over HDMI.
246
247 config VIDEO_VGA
248 boolean "VGA output support"
249 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
250 default n
251 ---help---
252 Say Y here to add support for outputting video over VGA.
253
254 config VIDEO_VGA_VIA_LCD
255 boolean "VGA via LCD controller support"
256 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
257 default n
258 ---help---
259 Say Y here to add support for external DACs connected to the parallel
260 LCD interface driving a VGA connector, such as found on the
261 Olimex A13 boards.
262
263 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
264 boolean "Force sync active high for VGA via LCD controller support"
265 depends on VIDEO_VGA_VIA_LCD
266 default n
267 ---help---
268 Say Y here if you've a board which uses opendrain drivers for the vga
269 hsync and vsync signals. Opendrain drivers cannot generate steep enough
270 positive edges for a stable video output, so on boards with opendrain
271 drivers the sync signals must always be active high.
272
273 config VIDEO_VGA_EXTERNAL_DAC_EN
274 string "LCD panel power enable pin"
275 depends on VIDEO_VGA_VIA_LCD
276 default ""
277 ---help---
278 Set the enable pin for the external VGA DAC. This takes a string in the
279 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
280
281 config VIDEO_LCD_MODE
282 string "LCD panel timing details"
283 depends on VIDEO
284 default ""
285 ---help---
286 LCD panel timing details string, leave empty if there is no LCD panel.
287 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
288 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
289
290 config VIDEO_LCD_DCLK_PHASE
291 int "LCD panel display clock phase"
292 depends on VIDEO
293 default 1
294 ---help---
295 Select LCD panel display clock phase shift, range 0-3.
296
297 config VIDEO_LCD_POWER
298 string "LCD panel power enable pin"
299 depends on VIDEO
300 default ""
301 ---help---
302 Set the power enable pin for the LCD panel. This takes a string in the
303 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
304
305 config VIDEO_LCD_BL_EN
306 string "LCD panel backlight enable pin"
307 depends on VIDEO
308 default ""
309 ---help---
310 Set the backlight enable pin for the LCD panel. This takes a string in the
311 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
312 port H.
313
314 config VIDEO_LCD_BL_PWM
315 string "LCD panel backlight pwm pin"
316 depends on VIDEO
317 default ""
318 ---help---
319 Set the backlight pwm pin for the LCD panel. This takes a string in the
320 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
321
322 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
323 bool "LCD panel backlight pwm is inverted"
324 depends on VIDEO
325 default y
326 ---help---
327 Set this if the backlight pwm output is active low.
328
329
330 # Note only one of these may be selected at a time! But hidden choices are
331 # not supported by Kconfig
332 config VIDEO_LCD_IF_PARALLEL
333 bool
334
335 config VIDEO_LCD_IF_LVDS
336 bool
337
338
339 choice
340 prompt "LCD panel support"
341 depends on VIDEO
342 ---help---
343 Select which type of LCD panel to support.
344
345 config VIDEO_LCD_PANEL_PARALLEL
346 bool "Generic parallel interface LCD panel"
347 select VIDEO_LCD_IF_PARALLEL
348
349 config VIDEO_LCD_PANEL_LVDS
350 bool "Generic lvds interface LCD panel"
351 select VIDEO_LCD_IF_LVDS
352
353 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
354 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
355 select VIDEO_LCD_SSD2828
356 select VIDEO_LCD_IF_PARALLEL
357 ---help---
358 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
359
360 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
361 bool "Hitachi tx18d42vm LCD panel"
362 select VIDEO_LCD_HITACHI_TX18D42VM
363 select VIDEO_LCD_IF_LVDS
364 ---help---
365 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
366
367 endchoice
368
369
370 config USB_MUSB_SUNXI
371 bool "Enable sunxi OTG / DRC USB controller in host mode"
372 default n
373 ---help---
374 Say y here to enable support for the sunxi OTG / DRC USB controller
375 used on almost all sunxi boards. Note currently u-boot can only have
376 one usb host controller enabled at a time, so enabling this on boards
377 which also use the ehci host controller will result in build errors.
378
379 config USB_KEYBOARD
380 boolean "Enable USB keyboard support"
381 default y
382 ---help---
383 Say Y here to add support for using a USB keyboard (typically used
384 in combination with a graphical console).
385
386 config GMAC_TX_DELAY
387 int "GMAC Transmit Clock Delay Chain"
388 default 0
389 ---help---
390 Set the GMAC Transmit Clock Delay Chain value.
391
392 endif