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[thirdparty/u-boot.git] / board / sunxi / board.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
11 */
12
13 #include <common.h>
14 #include <dm.h>
15 #include <env.h>
16 #include <hang.h>
17 #include <init.h>
18 #include <mmc.h>
19 #include <axp_pmic.h>
20 #include <generic-phy.h>
21 #include <phy-sun4i-usb.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/display.h>
25 #include <asm/arch/dram.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc.h>
28 #include <asm/arch/spl.h>
29 #include <u-boot/crc.h>
30 #ifndef CONFIG_ARM64
31 #include <asm/armv7.h>
32 #endif
33 #include <asm/gpio.h>
34 #include <asm/io.h>
35 #include <u-boot/crc.h>
36 #include <env_internal.h>
37 #include <linux/libfdt.h>
38 #include <nand.h>
39 #include <net.h>
40 #include <spl.h>
41 #include <sy8106a.h>
42 #include <asm/setup.h>
43
44 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
45 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
46 int soft_i2c_gpio_sda;
47 int soft_i2c_gpio_scl;
48
49 static int soft_i2c_board_init(void)
50 {
51 int ret;
52
53 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
54 if (soft_i2c_gpio_sda < 0) {
55 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
56 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
57 return soft_i2c_gpio_sda;
58 }
59 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
60 if (ret) {
61 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
63 return ret;
64 }
65
66 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
67 if (soft_i2c_gpio_scl < 0) {
68 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
69 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
70 return soft_i2c_gpio_scl;
71 }
72 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
73 if (ret) {
74 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
75 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
76 return ret;
77 }
78
79 return 0;
80 }
81 #else
82 static int soft_i2c_board_init(void) { return 0; }
83 #endif
84
85 DECLARE_GLOBAL_DATA_PTR;
86
87 void i2c_init_board(void)
88 {
89 #ifdef CONFIG_I2C0_ENABLE
90 #if defined(CONFIG_MACH_SUN4I) || \
91 defined(CONFIG_MACH_SUN5I) || \
92 defined(CONFIG_MACH_SUN7I) || \
93 defined(CONFIG_MACH_SUN8I_R40)
94 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
96 clock_twi_onoff(0, 1);
97 #elif defined(CONFIG_MACH_SUN6I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
100 clock_twi_onoff(0, 1);
101 #elif defined(CONFIG_MACH_SUN8I)
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
104 clock_twi_onoff(0, 1);
105 #elif defined(CONFIG_MACH_SUN50I)
106 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
107 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
108 clock_twi_onoff(0, 1);
109 #endif
110 #endif
111
112 #ifdef CONFIG_I2C1_ENABLE
113 #if defined(CONFIG_MACH_SUN4I) || \
114 defined(CONFIG_MACH_SUN7I) || \
115 defined(CONFIG_MACH_SUN8I_R40)
116 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
118 clock_twi_onoff(1, 1);
119 #elif defined(CONFIG_MACH_SUN5I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
122 clock_twi_onoff(1, 1);
123 #elif defined(CONFIG_MACH_SUN6I)
124 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
125 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
126 clock_twi_onoff(1, 1);
127 #elif defined(CONFIG_MACH_SUN8I)
128 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
129 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
130 clock_twi_onoff(1, 1);
131 #elif defined(CONFIG_MACH_SUN50I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
134 clock_twi_onoff(1, 1);
135 #endif
136 #endif
137
138 #ifdef CONFIG_I2C2_ENABLE
139 #if defined(CONFIG_MACH_SUN4I) || \
140 defined(CONFIG_MACH_SUN7I) || \
141 defined(CONFIG_MACH_SUN8I_R40)
142 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
143 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
144 clock_twi_onoff(2, 1);
145 #elif defined(CONFIG_MACH_SUN5I)
146 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
147 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
148 clock_twi_onoff(2, 1);
149 #elif defined(CONFIG_MACH_SUN6I)
150 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
151 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
152 clock_twi_onoff(2, 1);
153 #elif defined(CONFIG_MACH_SUN8I)
154 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
155 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
156 clock_twi_onoff(2, 1);
157 #elif defined(CONFIG_MACH_SUN50I)
158 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
159 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
160 clock_twi_onoff(2, 1);
161 #endif
162 #endif
163
164 #ifdef CONFIG_I2C3_ENABLE
165 #if defined(CONFIG_MACH_SUN6I)
166 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
167 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
168 clock_twi_onoff(3, 1);
169 #elif defined(CONFIG_MACH_SUN7I) || \
170 defined(CONFIG_MACH_SUN8I_R40)
171 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
172 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
173 clock_twi_onoff(3, 1);
174 #endif
175 #endif
176
177 #ifdef CONFIG_I2C4_ENABLE
178 #if defined(CONFIG_MACH_SUN7I) || \
179 defined(CONFIG_MACH_SUN8I_R40)
180 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
182 clock_twi_onoff(4, 1);
183 #endif
184 #endif
185
186 #ifdef CONFIG_R_I2C_ENABLE
187 #ifdef CONFIG_MACH_SUN50I
188 clock_twi_onoff(5, 1);
189 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
190 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
191 #else
192 clock_twi_onoff(5, 1);
193 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
194 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
195 #endif
196 #endif
197 }
198
199 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
200 enum env_location env_get_location(enum env_operation op, int prio)
201 {
202 switch (prio) {
203 case 0:
204 return ENVL_FAT;
205
206 case 1:
207 return ENVL_MMC;
208
209 default:
210 return ENVL_UNKNOWN;
211 }
212 }
213 #endif
214
215 #ifdef CONFIG_DM_MMC
216 static void mmc_pinmux_setup(int sdc);
217 #endif
218
219 /* add board specific code here */
220 int board_init(void)
221 {
222 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
223
224 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
225
226 #ifndef CONFIG_ARM64
227 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
228 debug("id_pfr1: 0x%08x\n", id_pfr1);
229 /* Generic Timer Extension available? */
230 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
231 uint32_t freq;
232
233 debug("Setting CNTFRQ\n");
234
235 /*
236 * CNTFRQ is a secure register, so we will crash if we try to
237 * write this from the non-secure world (read is OK, though).
238 * In case some bootcode has already set the correct value,
239 * we avoid the risk of writing to it.
240 */
241 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
242 if (freq != COUNTER_FREQUENCY) {
243 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
244 freq, COUNTER_FREQUENCY);
245 #ifdef CONFIG_NON_SECURE
246 printf("arch timer frequency is wrong, but cannot adjust it\n");
247 #else
248 asm volatile("mcr p15, 0, %0, c14, c0, 0"
249 : : "r"(COUNTER_FREQUENCY));
250 #endif
251 }
252 }
253 #endif /* !CONFIG_ARM64 */
254
255 ret = axp_gpio_init();
256 if (ret)
257 return ret;
258
259 #ifdef CONFIG_SATAPWR
260 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
261 gpio_request(satapwr_pin, "satapwr");
262 gpio_direction_output(satapwr_pin, 1);
263 /* Give attached sata device time to power-up to avoid link timeouts */
264 mdelay(500);
265 #endif
266 #ifdef CONFIG_MACPWR
267 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
268 gpio_request(macpwr_pin, "macpwr");
269 gpio_direction_output(macpwr_pin, 1);
270 #endif
271
272 #ifdef CONFIG_DM_I2C
273 /*
274 * Temporary workaround for enabling I2C clocks until proper sunxi DM
275 * clk, reset and pinctrl drivers land.
276 */
277 i2c_init_board();
278 #endif
279
280 #ifdef CONFIG_DM_MMC
281 /*
282 * Temporary workaround for enabling MMC clocks until a sunxi DM
283 * pinctrl driver lands.
284 */
285 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
286 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
287 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
288 #endif
289 #endif /* CONFIG_DM_MMC */
290
291 /* Uses dm gpio code so do this here and not in i2c_init_board() */
292 return soft_i2c_board_init();
293 }
294
295 /*
296 * On older SoCs the SPL is actually at address zero, so using NULL as
297 * an error value does not work.
298 */
299 #define INVALID_SPL_HEADER ((void *)~0UL)
300
301 static struct boot_file_head * get_spl_header(uint8_t req_version)
302 {
303 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
304 uint8_t spl_header_version = spl->spl_signature[3];
305
306 /* Is there really the SPL header (still) there? */
307 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
308 return INVALID_SPL_HEADER;
309
310 if (spl_header_version < req_version) {
311 printf("sunxi SPL version mismatch: expected %u, got %u\n",
312 req_version, spl_header_version);
313 return INVALID_SPL_HEADER;
314 }
315
316 return spl;
317 }
318
319 int dram_init(void)
320 {
321 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
322
323 if (spl == INVALID_SPL_HEADER)
324 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
325 PHYS_SDRAM_0_SIZE);
326 else
327 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
328
329 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
330 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
331
332 return 0;
333 }
334
335 #if defined(CONFIG_NAND_SUNXI)
336 static void nand_pinmux_setup(void)
337 {
338 unsigned int pin;
339
340 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
341 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
342
343 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
344 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
345 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
346 #endif
347 /* sun4i / sun7i do have a PC23, but it is not used for nand,
348 * only sun7i has a PC24 */
349 #ifdef CONFIG_MACH_SUN7I
350 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
351 #endif
352 }
353
354 static void nand_clock_setup(void)
355 {
356 struct sunxi_ccm_reg *const ccm =
357 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
358
359 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
360 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
361 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
362 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
363 #endif
364 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
365 }
366
367 void board_nand_init(void)
368 {
369 nand_pinmux_setup();
370 nand_clock_setup();
371 #ifndef CONFIG_SPL_BUILD
372 sunxi_nand_init();
373 #endif
374 }
375 #endif
376
377 #ifdef CONFIG_MMC
378 static void mmc_pinmux_setup(int sdc)
379 {
380 unsigned int pin;
381 __maybe_unused int pins;
382
383 switch (sdc) {
384 case 0:
385 /* SDC0: PF0-PF5 */
386 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
387 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
388 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
389 sunxi_gpio_set_drv(pin, 2);
390 }
391 break;
392
393 case 1:
394 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
395
396 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
397 defined(CONFIG_MACH_SUN8I_R40)
398 if (pins == SUNXI_GPIO_H) {
399 /* SDC1: PH22-PH-27 */
400 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
401 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
402 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
403 sunxi_gpio_set_drv(pin, 2);
404 }
405 } else {
406 /* SDC1: PG0-PG5 */
407 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
408 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
409 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
410 sunxi_gpio_set_drv(pin, 2);
411 }
412 }
413 #elif defined(CONFIG_MACH_SUN5I)
414 /* SDC1: PG3-PG8 */
415 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
416 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
417 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
418 sunxi_gpio_set_drv(pin, 2);
419 }
420 #elif defined(CONFIG_MACH_SUN6I)
421 /* SDC1: PG0-PG5 */
422 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
423 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
424 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
425 sunxi_gpio_set_drv(pin, 2);
426 }
427 #elif defined(CONFIG_MACH_SUN8I)
428 if (pins == SUNXI_GPIO_D) {
429 /* SDC1: PD2-PD7 */
430 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
431 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
432 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
433 sunxi_gpio_set_drv(pin, 2);
434 }
435 } else {
436 /* SDC1: PG0-PG5 */
437 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
438 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
439 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
440 sunxi_gpio_set_drv(pin, 2);
441 }
442 }
443 #endif
444 break;
445
446 case 2:
447 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
448
449 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
450 /* SDC2: PC6-PC11 */
451 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
452 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
453 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
454 sunxi_gpio_set_drv(pin, 2);
455 }
456 #elif defined(CONFIG_MACH_SUN5I)
457 if (pins == SUNXI_GPIO_E) {
458 /* SDC2: PE4-PE9 */
459 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
460 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
461 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
462 sunxi_gpio_set_drv(pin, 2);
463 }
464 } else {
465 /* SDC2: PC6-PC15 */
466 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
467 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
468 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
469 sunxi_gpio_set_drv(pin, 2);
470 }
471 }
472 #elif defined(CONFIG_MACH_SUN6I)
473 if (pins == SUNXI_GPIO_A) {
474 /* SDC2: PA9-PA14 */
475 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
476 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
477 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
478 sunxi_gpio_set_drv(pin, 2);
479 }
480 } else {
481 /* SDC2: PC6-PC15, PC24 */
482 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
483 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
484 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
485 sunxi_gpio_set_drv(pin, 2);
486 }
487
488 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
489 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
490 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
491 }
492 #elif defined(CONFIG_MACH_SUN8I_R40)
493 /* SDC2: PC6-PC15, PC24 */
494 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
495 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
498 }
499
500 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
501 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
502 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
503 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
504 /* SDC2: PC5-PC6, PC8-PC16 */
505 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
506 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
507 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
508 sunxi_gpio_set_drv(pin, 2);
509 }
510
511 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
512 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
513 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
514 sunxi_gpio_set_drv(pin, 2);
515 }
516 #elif defined(CONFIG_MACH_SUN50I_H6)
517 /* SDC2: PC4-PC14 */
518 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
519 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
520 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
521 sunxi_gpio_set_drv(pin, 2);
522 }
523 #elif defined(CONFIG_MACH_SUN9I)
524 /* SDC2: PC6-PC16 */
525 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
526 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
527 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
528 sunxi_gpio_set_drv(pin, 2);
529 }
530 #endif
531 break;
532
533 case 3:
534 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
535
536 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
537 defined(CONFIG_MACH_SUN8I_R40)
538 /* SDC3: PI4-PI9 */
539 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
540 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
541 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
542 sunxi_gpio_set_drv(pin, 2);
543 }
544 #elif defined(CONFIG_MACH_SUN6I)
545 if (pins == SUNXI_GPIO_A) {
546 /* SDC3: PA9-PA14 */
547 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
548 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
549 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
550 sunxi_gpio_set_drv(pin, 2);
551 }
552 } else {
553 /* SDC3: PC6-PC15, PC24 */
554 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
555 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
556 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
557 sunxi_gpio_set_drv(pin, 2);
558 }
559
560 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
561 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
562 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
563 }
564 #endif
565 break;
566
567 default:
568 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
569 break;
570 }
571 }
572
573 int board_mmc_init(bd_t *bis)
574 {
575 __maybe_unused struct mmc *mmc0, *mmc1;
576
577 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
578 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
579 if (!mmc0)
580 return -1;
581
582 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
583 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
584 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
585 if (!mmc1)
586 return -1;
587 #endif
588
589 return 0;
590 }
591 #endif
592
593 #ifdef CONFIG_SPL_BUILD
594
595 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
596 {
597 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
598
599 if (spl == INVALID_SPL_HEADER)
600 return;
601
602 /* Promote the header version for U-Boot proper, if needed. */
603 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
604 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
605
606 spl->dram_size = dram_size >> 20;
607 }
608
609 void sunxi_board_init(void)
610 {
611 int power_failed = 0;
612
613 #ifdef CONFIG_SY8106A_POWER
614 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
615 #endif
616
617 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
618 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
619 defined CONFIG_AXP818_POWER
620 power_failed = axp_init();
621
622 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
623 defined CONFIG_AXP818_POWER
624 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
625 #endif
626 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
627 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
628 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
629 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
630 #endif
631 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
632 defined CONFIG_AXP818_POWER
633 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
634 #endif
635
636 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
637 defined CONFIG_AXP818_POWER
638 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
639 #endif
640 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
641 #if !defined(CONFIG_AXP152_POWER)
642 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
643 #endif
644 #ifdef CONFIG_AXP209_POWER
645 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
646 #endif
647
648 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
649 defined(CONFIG_AXP818_POWER)
650 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
651 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
652 #if !defined CONFIG_AXP809_POWER
653 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
654 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
655 #endif
656 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
657 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
658 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
659 #endif
660
661 #ifdef CONFIG_AXP818_POWER
662 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
663 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
664 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
665 #endif
666
667 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
668 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
669 #endif
670 #endif
671 printf("DRAM:");
672 gd->ram_size = sunxi_dram_init();
673 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
674 if (!gd->ram_size)
675 hang();
676
677 sunxi_spl_store_dram_size(gd->ram_size);
678
679 /*
680 * Only clock up the CPU to full speed if we are reasonably
681 * assured it's being powered with suitable core voltage
682 */
683 if (!power_failed)
684 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
685 else
686 printf("Failed to set core voltage! Can't set CPU frequency\n");
687 }
688 #endif
689
690 #ifdef CONFIG_USB_GADGET
691 int g_dnl_board_usb_cable_connected(void)
692 {
693 struct udevice *dev;
694 struct phy phy;
695 int ret;
696
697 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
698 if (ret) {
699 pr_err("%s: Cannot find USB device\n", __func__);
700 return ret;
701 }
702
703 ret = generic_phy_get_by_name(dev, "usb", &phy);
704 if (ret) {
705 pr_err("failed to get %s USB PHY\n", dev->name);
706 return ret;
707 }
708
709 ret = generic_phy_init(&phy);
710 if (ret) {
711 pr_err("failed to init %s USB PHY\n", dev->name);
712 return ret;
713 }
714
715 ret = sun4i_usb_phy_vbus_detect(&phy);
716 if (ret == 1) {
717 pr_err("A charger is plugged into the OTG\n");
718 return -ENODEV;
719 }
720
721 return ret;
722 }
723 #endif
724
725 #ifdef CONFIG_SERIAL_TAG
726 void get_board_serial(struct tag_serialnr *serialnr)
727 {
728 char *serial_string;
729 unsigned long long serial;
730
731 serial_string = env_get("serial#");
732
733 if (serial_string) {
734 serial = simple_strtoull(serial_string, NULL, 16);
735
736 serialnr->high = (unsigned int) (serial >> 32);
737 serialnr->low = (unsigned int) (serial & 0xffffffff);
738 } else {
739 serialnr->high = 0;
740 serialnr->low = 0;
741 }
742 }
743 #endif
744
745 /*
746 * Check the SPL header for the "sunxi" variant. If found: parse values
747 * that might have been passed by the loader ("fel" utility), and update
748 * the environment accordingly.
749 */
750 static void parse_spl_header(const uint32_t spl_addr)
751 {
752 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
753
754 if (spl == INVALID_SPL_HEADER)
755 return;
756
757 if (!spl->fel_script_address)
758 return;
759
760 if (spl->fel_uEnv_length != 0) {
761 /*
762 * data is expected in uEnv.txt compatible format, so "env
763 * import -t" the string(s) at fel_script_address right away.
764 */
765 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
766 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
767 return;
768 }
769 /* otherwise assume .scr format (mkimage-type script) */
770 env_set_hex("fel_scriptaddr", spl->fel_script_address);
771 }
772
773 /*
774 * Note this function gets called multiple times.
775 * It must not make any changes to env variables which already exist.
776 */
777 static void setup_environment(const void *fdt)
778 {
779 char serial_string[17] = { 0 };
780 unsigned int sid[4];
781 uint8_t mac_addr[6];
782 char ethaddr[16];
783 int i, ret;
784
785 ret = sunxi_get_sid(sid);
786 if (ret == 0 && sid[0] != 0) {
787 /*
788 * The single words 1 - 3 of the SID have quite a few bits
789 * which are the same on many models, so we take a crc32
790 * of all 3 words, to get a more unique value.
791 *
792 * Note we only do this on newer SoCs as we cannot change
793 * the algorithm on older SoCs since those have been using
794 * fixed mac-addresses based on only using word 3 for a
795 * long time and changing a fixed mac-address with an
796 * u-boot update is not good.
797 */
798 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
799 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
800 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
801 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
802 #endif
803
804 /* Ensure the NIC specific bytes of the mac are not all 0 */
805 if ((sid[3] & 0xffffff) == 0)
806 sid[3] |= 0x800000;
807
808 for (i = 0; i < 4; i++) {
809 sprintf(ethaddr, "ethernet%d", i);
810 if (!fdt_get_alias(fdt, ethaddr))
811 continue;
812
813 if (i == 0)
814 strcpy(ethaddr, "ethaddr");
815 else
816 sprintf(ethaddr, "eth%daddr", i);
817
818 if (env_get(ethaddr))
819 continue;
820
821 /* Non OUI / registered MAC address */
822 mac_addr[0] = (i << 4) | 0x02;
823 mac_addr[1] = (sid[0] >> 0) & 0xff;
824 mac_addr[2] = (sid[3] >> 24) & 0xff;
825 mac_addr[3] = (sid[3] >> 16) & 0xff;
826 mac_addr[4] = (sid[3] >> 8) & 0xff;
827 mac_addr[5] = (sid[3] >> 0) & 0xff;
828
829 eth_env_set_enetaddr(ethaddr, mac_addr);
830 }
831
832 if (!env_get("serial#")) {
833 snprintf(serial_string, sizeof(serial_string),
834 "%08x%08x", sid[0], sid[3]);
835
836 env_set("serial#", serial_string);
837 }
838 }
839 }
840
841 int misc_init_r(void)
842 {
843 uint boot;
844
845 env_set("fel_booted", NULL);
846 env_set("fel_scriptaddr", NULL);
847 env_set("mmc_bootdev", NULL);
848
849 boot = sunxi_get_boot_device();
850 /* determine if we are running in FEL mode */
851 if (boot == BOOT_DEVICE_BOARD) {
852 env_set("fel_booted", "1");
853 parse_spl_header(SPL_ADDR);
854 /* or if we booted from MMC, and which one */
855 } else if (boot == BOOT_DEVICE_MMC1) {
856 env_set("mmc_bootdev", "0");
857 } else if (boot == BOOT_DEVICE_MMC2) {
858 env_set("mmc_bootdev", "1");
859 }
860
861 setup_environment(gd->fdt_blob);
862
863 #ifdef CONFIG_USB_ETHER
864 usb_ether_init();
865 #endif
866
867 return 0;
868 }
869
870 int ft_board_setup(void *blob, bd_t *bd)
871 {
872 int __maybe_unused r;
873
874 /*
875 * Call setup_environment again in case the boot fdt has
876 * ethernet aliases the u-boot copy does not have.
877 */
878 setup_environment(blob);
879
880 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
881 r = sunxi_simplefb_setup(blob);
882 if (r)
883 return r;
884 #endif
885 return 0;
886 }
887
888 #ifdef CONFIG_SPL_LOAD_FIT
889 int board_fit_config_name_match(const char *name)
890 {
891 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
892 const char *cmp_str = (const char *)spl;
893
894 /* Check if there is a DT name stored in the SPL header and use that. */
895 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
896 cmp_str += spl->dt_name_offset;
897 } else {
898 #ifdef CONFIG_DEFAULT_DEVICE_TREE
899 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
900 #else
901 return 0;
902 #endif
903 };
904
905 #ifdef CONFIG_PINE64_DT_SELECTION
906 /* Differentiate the two Pine64 board DTs by their DRAM size. */
907 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
908 if ((gd->ram_size > 512 * 1024 * 1024))
909 return !strstr(name, "plus");
910 else
911 return !!strstr(name, "plus");
912 } else {
913 return strcmp(name, cmp_str);
914 }
915 #endif
916 return strcmp(name, cmp_str);
917 }
918 #endif
"Das U-Boot" Source Tree