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common: Move RAM-sizing functions to init.h
[thirdparty/u-boot.git] / board / sunxi / board.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
11 */
12
13 #include <common.h>
14 #include <dm.h>
15 #include <env.h>
16 #include <init.h>
17 #include <mmc.h>
18 #include <axp_pmic.h>
19 #include <generic-phy.h>
20 #include <phy-sun4i-usb.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/display.h>
24 #include <asm/arch/dram.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/mmc.h>
27 #include <asm/arch/spl.h>
28 #include <u-boot/crc.h>
29 #ifndef CONFIG_ARM64
30 #include <asm/armv7.h>
31 #endif
32 #include <asm/gpio.h>
33 #include <asm/io.h>
34 #include <u-boot/crc.h>
35 #include <env_internal.h>
36 #include <linux/libfdt.h>
37 #include <nand.h>
38 #include <net.h>
39 #include <spl.h>
40 #include <sy8106a.h>
41 #include <asm/setup.h>
42
43 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
44 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
45 int soft_i2c_gpio_sda;
46 int soft_i2c_gpio_scl;
47
48 static int soft_i2c_board_init(void)
49 {
50 int ret;
51
52 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
53 if (soft_i2c_gpio_sda < 0) {
54 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
56 return soft_i2c_gpio_sda;
57 }
58 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
59 if (ret) {
60 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
61 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
62 return ret;
63 }
64
65 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
66 if (soft_i2c_gpio_scl < 0) {
67 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
69 return soft_i2c_gpio_scl;
70 }
71 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
72 if (ret) {
73 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
74 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
75 return ret;
76 }
77
78 return 0;
79 }
80 #else
81 static int soft_i2c_board_init(void) { return 0; }
82 #endif
83
84 DECLARE_GLOBAL_DATA_PTR;
85
86 void i2c_init_board(void)
87 {
88 #ifdef CONFIG_I2C0_ENABLE
89 #if defined(CONFIG_MACH_SUN4I) || \
90 defined(CONFIG_MACH_SUN5I) || \
91 defined(CONFIG_MACH_SUN7I) || \
92 defined(CONFIG_MACH_SUN8I_R40)
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
94 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
95 clock_twi_onoff(0, 1);
96 #elif defined(CONFIG_MACH_SUN6I)
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
99 clock_twi_onoff(0, 1);
100 #elif defined(CONFIG_MACH_SUN8I)
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
103 clock_twi_onoff(0, 1);
104 #elif defined(CONFIG_MACH_SUN50I)
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
106 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
107 clock_twi_onoff(0, 1);
108 #endif
109 #endif
110
111 #ifdef CONFIG_I2C1_ENABLE
112 #if defined(CONFIG_MACH_SUN4I) || \
113 defined(CONFIG_MACH_SUN7I) || \
114 defined(CONFIG_MACH_SUN8I_R40)
115 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
116 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
117 clock_twi_onoff(1, 1);
118 #elif defined(CONFIG_MACH_SUN5I)
119 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
120 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
121 clock_twi_onoff(1, 1);
122 #elif defined(CONFIG_MACH_SUN6I)
123 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
124 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
125 clock_twi_onoff(1, 1);
126 #elif defined(CONFIG_MACH_SUN8I)
127 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
128 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
129 clock_twi_onoff(1, 1);
130 #elif defined(CONFIG_MACH_SUN50I)
131 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
133 clock_twi_onoff(1, 1);
134 #endif
135 #endif
136
137 #ifdef CONFIG_I2C2_ENABLE
138 #if defined(CONFIG_MACH_SUN4I) || \
139 defined(CONFIG_MACH_SUN7I) || \
140 defined(CONFIG_MACH_SUN8I_R40)
141 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
142 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
143 clock_twi_onoff(2, 1);
144 #elif defined(CONFIG_MACH_SUN5I)
145 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
146 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
147 clock_twi_onoff(2, 1);
148 #elif defined(CONFIG_MACH_SUN6I)
149 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
150 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
151 clock_twi_onoff(2, 1);
152 #elif defined(CONFIG_MACH_SUN8I)
153 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
154 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
155 clock_twi_onoff(2, 1);
156 #elif defined(CONFIG_MACH_SUN50I)
157 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
158 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
159 clock_twi_onoff(2, 1);
160 #endif
161 #endif
162
163 #ifdef CONFIG_I2C3_ENABLE
164 #if defined(CONFIG_MACH_SUN6I)
165 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
166 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
167 clock_twi_onoff(3, 1);
168 #elif defined(CONFIG_MACH_SUN7I) || \
169 defined(CONFIG_MACH_SUN8I_R40)
170 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
171 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
172 clock_twi_onoff(3, 1);
173 #endif
174 #endif
175
176 #ifdef CONFIG_I2C4_ENABLE
177 #if defined(CONFIG_MACH_SUN7I) || \
178 defined(CONFIG_MACH_SUN8I_R40)
179 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
180 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
181 clock_twi_onoff(4, 1);
182 #endif
183 #endif
184
185 #ifdef CONFIG_R_I2C_ENABLE
186 #ifdef CONFIG_MACH_SUN50I
187 clock_twi_onoff(5, 1);
188 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
189 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
190 #else
191 clock_twi_onoff(5, 1);
192 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
193 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
194 #endif
195 #endif
196 }
197
198 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
199 enum env_location env_get_location(enum env_operation op, int prio)
200 {
201 switch (prio) {
202 case 0:
203 return ENVL_FAT;
204
205 case 1:
206 return ENVL_MMC;
207
208 default:
209 return ENVL_UNKNOWN;
210 }
211 }
212 #endif
213
214 #ifdef CONFIG_DM_MMC
215 static void mmc_pinmux_setup(int sdc);
216 #endif
217
218 /* add board specific code here */
219 int board_init(void)
220 {
221 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
222
223 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
224
225 #ifndef CONFIG_ARM64
226 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
227 debug("id_pfr1: 0x%08x\n", id_pfr1);
228 /* Generic Timer Extension available? */
229 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
230 uint32_t freq;
231
232 debug("Setting CNTFRQ\n");
233
234 /*
235 * CNTFRQ is a secure register, so we will crash if we try to
236 * write this from the non-secure world (read is OK, though).
237 * In case some bootcode has already set the correct value,
238 * we avoid the risk of writing to it.
239 */
240 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
241 if (freq != COUNTER_FREQUENCY) {
242 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
243 freq, COUNTER_FREQUENCY);
244 #ifdef CONFIG_NON_SECURE
245 printf("arch timer frequency is wrong, but cannot adjust it\n");
246 #else
247 asm volatile("mcr p15, 0, %0, c14, c0, 0"
248 : : "r"(COUNTER_FREQUENCY));
249 #endif
250 }
251 }
252 #endif /* !CONFIG_ARM64 */
253
254 ret = axp_gpio_init();
255 if (ret)
256 return ret;
257
258 #ifdef CONFIG_SATAPWR
259 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
260 gpio_request(satapwr_pin, "satapwr");
261 gpio_direction_output(satapwr_pin, 1);
262 /* Give attached sata device time to power-up to avoid link timeouts */
263 mdelay(500);
264 #endif
265 #ifdef CONFIG_MACPWR
266 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
267 gpio_request(macpwr_pin, "macpwr");
268 gpio_direction_output(macpwr_pin, 1);
269 #endif
270
271 #ifdef CONFIG_DM_I2C
272 /*
273 * Temporary workaround for enabling I2C clocks until proper sunxi DM
274 * clk, reset and pinctrl drivers land.
275 */
276 i2c_init_board();
277 #endif
278
279 #ifdef CONFIG_DM_MMC
280 /*
281 * Temporary workaround for enabling MMC clocks until a sunxi DM
282 * pinctrl driver lands.
283 */
284 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
285 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
286 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
287 #endif
288 #endif /* CONFIG_DM_MMC */
289
290 /* Uses dm gpio code so do this here and not in i2c_init_board() */
291 return soft_i2c_board_init();
292 }
293
294 /*
295 * On older SoCs the SPL is actually at address zero, so using NULL as
296 * an error value does not work.
297 */
298 #define INVALID_SPL_HEADER ((void *)~0UL)
299
300 static struct boot_file_head * get_spl_header(uint8_t req_version)
301 {
302 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
303 uint8_t spl_header_version = spl->spl_signature[3];
304
305 /* Is there really the SPL header (still) there? */
306 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
307 return INVALID_SPL_HEADER;
308
309 if (spl_header_version < req_version) {
310 printf("sunxi SPL version mismatch: expected %u, got %u\n",
311 req_version, spl_header_version);
312 return INVALID_SPL_HEADER;
313 }
314
315 return spl;
316 }
317
318 int dram_init(void)
319 {
320 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
321
322 if (spl == INVALID_SPL_HEADER)
323 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
324 PHYS_SDRAM_0_SIZE);
325 else
326 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
327
328 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
329 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
330
331 return 0;
332 }
333
334 #if defined(CONFIG_NAND_SUNXI)
335 static void nand_pinmux_setup(void)
336 {
337 unsigned int pin;
338
339 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
340 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
341
342 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
343 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
344 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
345 #endif
346 /* sun4i / sun7i do have a PC23, but it is not used for nand,
347 * only sun7i has a PC24 */
348 #ifdef CONFIG_MACH_SUN7I
349 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
350 #endif
351 }
352
353 static void nand_clock_setup(void)
354 {
355 struct sunxi_ccm_reg *const ccm =
356 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
357
358 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
359 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
360 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
361 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
362 #endif
363 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
364 }
365
366 void board_nand_init(void)
367 {
368 nand_pinmux_setup();
369 nand_clock_setup();
370 #ifndef CONFIG_SPL_BUILD
371 sunxi_nand_init();
372 #endif
373 }
374 #endif
375
376 #ifdef CONFIG_MMC
377 static void mmc_pinmux_setup(int sdc)
378 {
379 unsigned int pin;
380 __maybe_unused int pins;
381
382 switch (sdc) {
383 case 0:
384 /* SDC0: PF0-PF5 */
385 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
386 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
387 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
388 sunxi_gpio_set_drv(pin, 2);
389 }
390 break;
391
392 case 1:
393 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
394
395 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
396 defined(CONFIG_MACH_SUN8I_R40)
397 if (pins == SUNXI_GPIO_H) {
398 /* SDC1: PH22-PH-27 */
399 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
400 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
401 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
402 sunxi_gpio_set_drv(pin, 2);
403 }
404 } else {
405 /* SDC1: PG0-PG5 */
406 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
407 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
408 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
409 sunxi_gpio_set_drv(pin, 2);
410 }
411 }
412 #elif defined(CONFIG_MACH_SUN5I)
413 /* SDC1: PG3-PG8 */
414 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
415 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
416 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
417 sunxi_gpio_set_drv(pin, 2);
418 }
419 #elif defined(CONFIG_MACH_SUN6I)
420 /* SDC1: PG0-PG5 */
421 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
422 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
423 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(pin, 2);
425 }
426 #elif defined(CONFIG_MACH_SUN8I)
427 if (pins == SUNXI_GPIO_D) {
428 /* SDC1: PD2-PD7 */
429 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
430 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
431 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
432 sunxi_gpio_set_drv(pin, 2);
433 }
434 } else {
435 /* SDC1: PG0-PG5 */
436 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
437 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
438 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
439 sunxi_gpio_set_drv(pin, 2);
440 }
441 }
442 #endif
443 break;
444
445 case 2:
446 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
447
448 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
449 /* SDC2: PC6-PC11 */
450 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
451 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
452 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(pin, 2);
454 }
455 #elif defined(CONFIG_MACH_SUN5I)
456 if (pins == SUNXI_GPIO_E) {
457 /* SDC2: PE4-PE9 */
458 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
459 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
460 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
461 sunxi_gpio_set_drv(pin, 2);
462 }
463 } else {
464 /* SDC2: PC6-PC15 */
465 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
466 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
467 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
468 sunxi_gpio_set_drv(pin, 2);
469 }
470 }
471 #elif defined(CONFIG_MACH_SUN6I)
472 if (pins == SUNXI_GPIO_A) {
473 /* SDC2: PA9-PA14 */
474 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
475 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
476 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
477 sunxi_gpio_set_drv(pin, 2);
478 }
479 } else {
480 /* SDC2: PC6-PC15, PC24 */
481 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
482 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
483 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
484 sunxi_gpio_set_drv(pin, 2);
485 }
486
487 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
488 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
489 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
490 }
491 #elif defined(CONFIG_MACH_SUN8I_R40)
492 /* SDC2: PC6-PC15, PC24 */
493 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
494 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
495 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
496 sunxi_gpio_set_drv(pin, 2);
497 }
498
499 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
500 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
501 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
502 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
503 /* SDC2: PC5-PC6, PC8-PC16 */
504 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
505 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
506 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
507 sunxi_gpio_set_drv(pin, 2);
508 }
509
510 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
511 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
512 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
513 sunxi_gpio_set_drv(pin, 2);
514 }
515 #elif defined(CONFIG_MACH_SUN50I_H6)
516 /* SDC2: PC4-PC14 */
517 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
518 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
519 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
520 sunxi_gpio_set_drv(pin, 2);
521 }
522 #elif defined(CONFIG_MACH_SUN9I)
523 /* SDC2: PC6-PC16 */
524 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
525 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
526 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
527 sunxi_gpio_set_drv(pin, 2);
528 }
529 #endif
530 break;
531
532 case 3:
533 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
534
535 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
536 defined(CONFIG_MACH_SUN8I_R40)
537 /* SDC3: PI4-PI9 */
538 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
539 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
540 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
541 sunxi_gpio_set_drv(pin, 2);
542 }
543 #elif defined(CONFIG_MACH_SUN6I)
544 if (pins == SUNXI_GPIO_A) {
545 /* SDC3: PA9-PA14 */
546 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
547 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
548 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
549 sunxi_gpio_set_drv(pin, 2);
550 }
551 } else {
552 /* SDC3: PC6-PC15, PC24 */
553 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
554 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
555 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
556 sunxi_gpio_set_drv(pin, 2);
557 }
558
559 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
560 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
561 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
562 }
563 #endif
564 break;
565
566 default:
567 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
568 break;
569 }
570 }
571
572 int board_mmc_init(bd_t *bis)
573 {
574 __maybe_unused struct mmc *mmc0, *mmc1;
575
576 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
577 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
578 if (!mmc0)
579 return -1;
580
581 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
582 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
583 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
584 if (!mmc1)
585 return -1;
586 #endif
587
588 return 0;
589 }
590 #endif
591
592 #ifdef CONFIG_SPL_BUILD
593
594 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
595 {
596 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
597
598 if (spl == INVALID_SPL_HEADER)
599 return;
600
601 /* Promote the header version for U-Boot proper, if needed. */
602 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
603 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
604
605 spl->dram_size = dram_size >> 20;
606 }
607
608 void sunxi_board_init(void)
609 {
610 int power_failed = 0;
611
612 #ifdef CONFIG_SY8106A_POWER
613 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
614 #endif
615
616 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
617 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
618 defined CONFIG_AXP818_POWER
619 power_failed = axp_init();
620
621 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
622 defined CONFIG_AXP818_POWER
623 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
624 #endif
625 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
626 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
627 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
628 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
629 #endif
630 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
631 defined CONFIG_AXP818_POWER
632 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
633 #endif
634
635 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
636 defined CONFIG_AXP818_POWER
637 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
638 #endif
639 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
640 #if !defined(CONFIG_AXP152_POWER)
641 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
642 #endif
643 #ifdef CONFIG_AXP209_POWER
644 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
645 #endif
646
647 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
648 defined(CONFIG_AXP818_POWER)
649 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
650 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
651 #if !defined CONFIG_AXP809_POWER
652 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
653 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
654 #endif
655 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
656 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
657 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
658 #endif
659
660 #ifdef CONFIG_AXP818_POWER
661 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
662 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
663 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
664 #endif
665
666 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
667 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
668 #endif
669 #endif
670 printf("DRAM:");
671 gd->ram_size = sunxi_dram_init();
672 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
673 if (!gd->ram_size)
674 hang();
675
676 sunxi_spl_store_dram_size(gd->ram_size);
677
678 /*
679 * Only clock up the CPU to full speed if we are reasonably
680 * assured it's being powered with suitable core voltage
681 */
682 if (!power_failed)
683 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
684 else
685 printf("Failed to set core voltage! Can't set CPU frequency\n");
686 }
687 #endif
688
689 #ifdef CONFIG_USB_GADGET
690 int g_dnl_board_usb_cable_connected(void)
691 {
692 struct udevice *dev;
693 struct phy phy;
694 int ret;
695
696 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
697 if (ret) {
698 pr_err("%s: Cannot find USB device\n", __func__);
699 return ret;
700 }
701
702 ret = generic_phy_get_by_name(dev, "usb", &phy);
703 if (ret) {
704 pr_err("failed to get %s USB PHY\n", dev->name);
705 return ret;
706 }
707
708 ret = generic_phy_init(&phy);
709 if (ret) {
710 pr_err("failed to init %s USB PHY\n", dev->name);
711 return ret;
712 }
713
714 ret = sun4i_usb_phy_vbus_detect(&phy);
715 if (ret == 1) {
716 pr_err("A charger is plugged into the OTG\n");
717 return -ENODEV;
718 }
719
720 return ret;
721 }
722 #endif
723
724 #ifdef CONFIG_SERIAL_TAG
725 void get_board_serial(struct tag_serialnr *serialnr)
726 {
727 char *serial_string;
728 unsigned long long serial;
729
730 serial_string = env_get("serial#");
731
732 if (serial_string) {
733 serial = simple_strtoull(serial_string, NULL, 16);
734
735 serialnr->high = (unsigned int) (serial >> 32);
736 serialnr->low = (unsigned int) (serial & 0xffffffff);
737 } else {
738 serialnr->high = 0;
739 serialnr->low = 0;
740 }
741 }
742 #endif
743
744 /*
745 * Check the SPL header for the "sunxi" variant. If found: parse values
746 * that might have been passed by the loader ("fel" utility), and update
747 * the environment accordingly.
748 */
749 static void parse_spl_header(const uint32_t spl_addr)
750 {
751 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
752
753 if (spl == INVALID_SPL_HEADER)
754 return;
755
756 if (!spl->fel_script_address)
757 return;
758
759 if (spl->fel_uEnv_length != 0) {
760 /*
761 * data is expected in uEnv.txt compatible format, so "env
762 * import -t" the string(s) at fel_script_address right away.
763 */
764 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
765 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
766 return;
767 }
768 /* otherwise assume .scr format (mkimage-type script) */
769 env_set_hex("fel_scriptaddr", spl->fel_script_address);
770 }
771
772 /*
773 * Note this function gets called multiple times.
774 * It must not make any changes to env variables which already exist.
775 */
776 static void setup_environment(const void *fdt)
777 {
778 char serial_string[17] = { 0 };
779 unsigned int sid[4];
780 uint8_t mac_addr[6];
781 char ethaddr[16];
782 int i, ret;
783
784 ret = sunxi_get_sid(sid);
785 if (ret == 0 && sid[0] != 0) {
786 /*
787 * The single words 1 - 3 of the SID have quite a few bits
788 * which are the same on many models, so we take a crc32
789 * of all 3 words, to get a more unique value.
790 *
791 * Note we only do this on newer SoCs as we cannot change
792 * the algorithm on older SoCs since those have been using
793 * fixed mac-addresses based on only using word 3 for a
794 * long time and changing a fixed mac-address with an
795 * u-boot update is not good.
796 */
797 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
798 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
799 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
800 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
801 #endif
802
803 /* Ensure the NIC specific bytes of the mac are not all 0 */
804 if ((sid[3] & 0xffffff) == 0)
805 sid[3] |= 0x800000;
806
807 for (i = 0; i < 4; i++) {
808 sprintf(ethaddr, "ethernet%d", i);
809 if (!fdt_get_alias(fdt, ethaddr))
810 continue;
811
812 if (i == 0)
813 strcpy(ethaddr, "ethaddr");
814 else
815 sprintf(ethaddr, "eth%daddr", i);
816
817 if (env_get(ethaddr))
818 continue;
819
820 /* Non OUI / registered MAC address */
821 mac_addr[0] = (i << 4) | 0x02;
822 mac_addr[1] = (sid[0] >> 0) & 0xff;
823 mac_addr[2] = (sid[3] >> 24) & 0xff;
824 mac_addr[3] = (sid[3] >> 16) & 0xff;
825 mac_addr[4] = (sid[3] >> 8) & 0xff;
826 mac_addr[5] = (sid[3] >> 0) & 0xff;
827
828 eth_env_set_enetaddr(ethaddr, mac_addr);
829 }
830
831 if (!env_get("serial#")) {
832 snprintf(serial_string, sizeof(serial_string),
833 "%08x%08x", sid[0], sid[3]);
834
835 env_set("serial#", serial_string);
836 }
837 }
838 }
839
840 int misc_init_r(void)
841 {
842 uint boot;
843
844 env_set("fel_booted", NULL);
845 env_set("fel_scriptaddr", NULL);
846 env_set("mmc_bootdev", NULL);
847
848 boot = sunxi_get_boot_device();
849 /* determine if we are running in FEL mode */
850 if (boot == BOOT_DEVICE_BOARD) {
851 env_set("fel_booted", "1");
852 parse_spl_header(SPL_ADDR);
853 /* or if we booted from MMC, and which one */
854 } else if (boot == BOOT_DEVICE_MMC1) {
855 env_set("mmc_bootdev", "0");
856 } else if (boot == BOOT_DEVICE_MMC2) {
857 env_set("mmc_bootdev", "1");
858 }
859
860 setup_environment(gd->fdt_blob);
861
862 #ifdef CONFIG_USB_ETHER
863 usb_ether_init();
864 #endif
865
866 return 0;
867 }
868
869 int ft_board_setup(void *blob, bd_t *bd)
870 {
871 int __maybe_unused r;
872
873 /*
874 * Call setup_environment again in case the boot fdt has
875 * ethernet aliases the u-boot copy does not have.
876 */
877 setup_environment(blob);
878
879 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
880 r = sunxi_simplefb_setup(blob);
881 if (r)
882 return r;
883 #endif
884 return 0;
885 }
886
887 #ifdef CONFIG_SPL_LOAD_FIT
888 int board_fit_config_name_match(const char *name)
889 {
890 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
891 const char *cmp_str = (const char *)spl;
892
893 /* Check if there is a DT name stored in the SPL header and use that. */
894 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
895 cmp_str += spl->dt_name_offset;
896 } else {
897 #ifdef CONFIG_DEFAULT_DEVICE_TREE
898 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
899 #else
900 return 0;
901 #endif
902 };
903
904 #ifdef CONFIG_PINE64_DT_SELECTION
905 /* Differentiate the two Pine64 board DTs by their DRAM size. */
906 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
907 if ((gd->ram_size > 512 * 1024 * 1024))
908 return !strstr(name, "plus");
909 else
910 return !!strstr(name, "plus");
911 } else {
912 return strcmp(name, cmp_str);
913 }
914 #endif
915 return strcmp(name, cmp_str);
916 }
917 #endif
"Das U-Boot" Source Tree