2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/usb_phy.h>
25 #include <asm/armv7.h>
33 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
34 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
35 int soft_i2c_gpio_sda
;
36 int soft_i2c_gpio_scl
;
38 static int soft_i2c_board_init(void)
42 soft_i2c_gpio_sda
= sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA
);
43 if (soft_i2c_gpio_sda
< 0) {
44 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
45 CONFIG_VIDEO_LCD_PANEL_I2C_SDA
, soft_i2c_gpio_sda
);
46 return soft_i2c_gpio_sda
;
48 ret
= gpio_request(soft_i2c_gpio_sda
, "soft-i2c-sda");
50 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
51 CONFIG_VIDEO_LCD_PANEL_I2C_SDA
, ret
);
55 soft_i2c_gpio_scl
= sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL
);
56 if (soft_i2c_gpio_scl
< 0) {
57 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
58 CONFIG_VIDEO_LCD_PANEL_I2C_SCL
, soft_i2c_gpio_scl
);
59 return soft_i2c_gpio_scl
;
61 ret
= gpio_request(soft_i2c_gpio_scl
, "soft-i2c-scl");
63 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
64 CONFIG_VIDEO_LCD_PANEL_I2C_SCL
, ret
);
71 static int soft_i2c_board_init(void) { return 0; }
74 DECLARE_GLOBAL_DATA_PTR
;
76 /* add board specific code here */
79 __maybe_unused
int id_pfr1
, ret
;
81 gd
->bd
->bi_boot_params
= (PHYS_SDRAM_0
+ 0x100);
84 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1
));
85 debug("id_pfr1: 0x%08x\n", id_pfr1
);
86 /* Generic Timer Extension available? */
87 if ((id_pfr1
>> CPUID_ARM_GENTIMER_SHIFT
) & 0xf) {
90 debug("Setting CNTFRQ\n");
93 * CNTFRQ is a secure register, so we will crash if we try to
94 * write this from the non-secure world (read is OK, though).
95 * In case some bootcode has already set the correct value,
96 * we avoid the risk of writing to it.
98 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq
));
99 if (freq
!= CONFIG_TIMER_CLK_FREQ
) {
100 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
101 freq
, CONFIG_TIMER_CLK_FREQ
);
102 #ifdef CONFIG_NON_SECURE
103 printf("arch timer frequency is wrong, but cannot adjust it\n");
105 asm volatile("mcr p15, 0, %0, c14, c0, 0"
106 : : "r"(CONFIG_TIMER_CLK_FREQ
));
110 #endif /* !CONFIG_ARM64 */
112 ret
= axp_gpio_init();
116 #ifdef CONFIG_SATAPWR
117 gpio_request(CONFIG_SATAPWR
, "satapwr");
118 gpio_direction_output(CONFIG_SATAPWR
, 1);
121 gpio_request(CONFIG_MACPWR
, "macpwr");
122 gpio_direction_output(CONFIG_MACPWR
, 1);
125 /* Uses dm gpio code so do this here and not in i2c_init_board() */
126 return soft_i2c_board_init();
131 gd
->ram_size
= get_ram_size((long *)PHYS_SDRAM_0
, PHYS_SDRAM_0_SIZE
);
136 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
137 static void nand_pinmux_setup(void)
141 for (pin
= SUNXI_GPC(0); pin
<= SUNXI_GPC(19); pin
++)
142 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_NAND
);
144 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
145 for (pin
= SUNXI_GPC(20); pin
<= SUNXI_GPC(22); pin
++)
146 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_NAND
);
148 /* sun4i / sun7i do have a PC23, but it is not used for nand,
149 * only sun7i has a PC24 */
150 #ifdef CONFIG_MACH_SUN7I
151 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND
);
155 static void nand_clock_setup(void)
157 struct sunxi_ccm_reg
*const ccm
=
158 (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
160 setbits_le32(&ccm
->ahb_gate0
, (CLK_GATE_OPEN
<< AHB_GATE_OFFSET_NAND0
));
161 #ifdef CONFIG_MACH_SUN9I
162 setbits_le32(&ccm
->ahb_gate1
, (1 << AHB_GATE_OFFSET_DMA
));
164 setbits_le32(&ccm
->ahb_gate0
, (1 << AHB_GATE_OFFSET_DMA
));
166 setbits_le32(&ccm
->nand0_clk_cfg
, CCM_NAND_CTRL_ENABLE
| AHB_DIV_1
);
169 void board_nand_init(void)
176 #ifdef CONFIG_GENERIC_MMC
177 static void mmc_pinmux_setup(int sdc
)
180 __maybe_unused
int pins
;
185 for (pin
= SUNXI_GPF(0); pin
<= SUNXI_GPF(5); pin
++) {
186 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPF_SDC0
);
187 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
188 sunxi_gpio_set_drv(pin
, 2);
193 pins
= sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS
);
195 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
196 if (pins
== SUNXI_GPIO_H
) {
197 /* SDC1: PH22-PH-27 */
198 for (pin
= SUNXI_GPH(22); pin
<= SUNXI_GPH(27); pin
++) {
199 sunxi_gpio_set_cfgpin(pin
, SUN4I_GPH_SDC1
);
200 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
201 sunxi_gpio_set_drv(pin
, 2);
205 for (pin
= SUNXI_GPG(0); pin
<= SUNXI_GPG(5); pin
++) {
206 sunxi_gpio_set_cfgpin(pin
, SUN4I_GPG_SDC1
);
207 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
208 sunxi_gpio_set_drv(pin
, 2);
211 #elif defined(CONFIG_MACH_SUN5I)
213 for (pin
= SUNXI_GPG(3); pin
<= SUNXI_GPG(8); pin
++) {
214 sunxi_gpio_set_cfgpin(pin
, SUN5I_GPG_SDC1
);
215 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
216 sunxi_gpio_set_drv(pin
, 2);
218 #elif defined(CONFIG_MACH_SUN6I)
220 for (pin
= SUNXI_GPG(0); pin
<= SUNXI_GPG(5); pin
++) {
221 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPG_SDC1
);
222 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
223 sunxi_gpio_set_drv(pin
, 2);
225 #elif defined(CONFIG_MACH_SUN8I)
226 if (pins
== SUNXI_GPIO_D
) {
228 for (pin
= SUNXI_GPD(2); pin
<= SUNXI_GPD(7); pin
++) {
229 sunxi_gpio_set_cfgpin(pin
, SUN8I_GPD_SDC1
);
230 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
231 sunxi_gpio_set_drv(pin
, 2);
235 for (pin
= SUNXI_GPG(0); pin
<= SUNXI_GPG(5); pin
++) {
236 sunxi_gpio_set_cfgpin(pin
, SUN8I_GPG_SDC1
);
237 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
238 sunxi_gpio_set_drv(pin
, 2);
245 pins
= sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS
);
247 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
249 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(11); pin
++) {
250 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
251 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
252 sunxi_gpio_set_drv(pin
, 2);
254 #elif defined(CONFIG_MACH_SUN5I)
255 if (pins
== SUNXI_GPIO_E
) {
257 for (pin
= SUNXI_GPE(4); pin
<= SUNXI_GPD(9); pin
++) {
258 sunxi_gpio_set_cfgpin(pin
, SUN5I_GPE_SDC2
);
259 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
260 sunxi_gpio_set_drv(pin
, 2);
264 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(15); pin
++) {
265 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
266 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
267 sunxi_gpio_set_drv(pin
, 2);
270 #elif defined(CONFIG_MACH_SUN6I)
271 if (pins
== SUNXI_GPIO_A
) {
273 for (pin
= SUNXI_GPA(9); pin
<= SUNXI_GPA(14); pin
++) {
274 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPA_SDC2
);
275 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
276 sunxi_gpio_set_drv(pin
, 2);
279 /* SDC2: PC6-PC15, PC24 */
280 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(15); pin
++) {
281 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
282 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
283 sunxi_gpio_set_drv(pin
, 2);
286 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2
);
287 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP
);
288 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
290 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
291 /* SDC2: PC5-PC6, PC8-PC16 */
292 for (pin
= SUNXI_GPC(5); pin
<= SUNXI_GPC(6); pin
++) {
293 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
294 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
295 sunxi_gpio_set_drv(pin
, 2);
298 for (pin
= SUNXI_GPC(8); pin
<= SUNXI_GPC(16); pin
++) {
299 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
300 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
301 sunxi_gpio_set_drv(pin
, 2);
307 pins
= sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS
);
309 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
311 for (pin
= SUNXI_GPI(4); pin
<= SUNXI_GPI(9); pin
++) {
312 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPI_SDC3
);
313 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
314 sunxi_gpio_set_drv(pin
, 2);
316 #elif defined(CONFIG_MACH_SUN6I)
317 if (pins
== SUNXI_GPIO_A
) {
319 for (pin
= SUNXI_GPA(9); pin
<= SUNXI_GPA(14); pin
++) {
320 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPA_SDC3
);
321 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
322 sunxi_gpio_set_drv(pin
, 2);
325 /* SDC3: PC6-PC15, PC24 */
326 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(15); pin
++) {
327 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPC_SDC3
);
328 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
329 sunxi_gpio_set_drv(pin
, 2);
332 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3
);
333 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP
);
334 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
340 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc
);
345 int board_mmc_init(bd_t
*bis
)
347 __maybe_unused
struct mmc
*mmc0
, *mmc1
;
348 __maybe_unused
char buf
[512];
350 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT
);
351 mmc0
= sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT
);
355 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
356 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA
);
357 mmc1
= sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA
);
362 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
364 * On systems with an emmc (mmc2), figure out if we are booting from
365 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
366 * are searched there first. Note we only do this for u-boot proper,
367 * not for the SPL, see spl_boot_device().
369 if (!sunxi_mmc_has_egon_boot_signature(mmc0
) &&
370 sunxi_mmc_has_egon_boot_signature(mmc1
)) {
371 /* Booting from emmc / mmc2, swap */
372 mmc0
->block_dev
.devnum
= 1;
373 mmc1
->block_dev
.devnum
= 0;
381 void i2c_init_board(void)
383 #ifdef CONFIG_I2C0_ENABLE
384 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
385 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0
);
386 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0
);
387 clock_twi_onoff(0, 1);
388 #elif defined(CONFIG_MACH_SUN6I)
389 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0
);
390 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0
);
391 clock_twi_onoff(0, 1);
392 #elif defined(CONFIG_MACH_SUN8I)
393 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0
);
394 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0
);
395 clock_twi_onoff(0, 1);
399 #ifdef CONFIG_I2C1_ENABLE
400 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
401 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1
);
402 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1
);
403 clock_twi_onoff(1, 1);
404 #elif defined(CONFIG_MACH_SUN5I)
405 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1
);
406 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1
);
407 clock_twi_onoff(1, 1);
408 #elif defined(CONFIG_MACH_SUN6I)
409 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1
);
410 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1
);
411 clock_twi_onoff(1, 1);
412 #elif defined(CONFIG_MACH_SUN8I)
413 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1
);
414 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1
);
415 clock_twi_onoff(1, 1);
419 #ifdef CONFIG_I2C2_ENABLE
420 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
421 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2
);
422 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2
);
423 clock_twi_onoff(2, 1);
424 #elif defined(CONFIG_MACH_SUN5I)
425 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2
);
426 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2
);
427 clock_twi_onoff(2, 1);
428 #elif defined(CONFIG_MACH_SUN6I)
429 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2
);
430 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2
);
431 clock_twi_onoff(2, 1);
432 #elif defined(CONFIG_MACH_SUN8I)
433 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2
);
434 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2
);
435 clock_twi_onoff(2, 1);
439 #ifdef CONFIG_I2C3_ENABLE
440 #if defined(CONFIG_MACH_SUN6I)
441 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3
);
442 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3
);
443 clock_twi_onoff(3, 1);
444 #elif defined(CONFIG_MACH_SUN7I)
445 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3
);
446 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3
);
447 clock_twi_onoff(3, 1);
451 #ifdef CONFIG_I2C4_ENABLE
452 #if defined(CONFIG_MACH_SUN7I)
453 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4
);
454 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4
);
455 clock_twi_onoff(4, 1);
459 #ifdef CONFIG_R_I2C_ENABLE
460 clock_twi_onoff(5, 1);
461 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI
);
462 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI
);
466 #ifdef CONFIG_SPL_BUILD
467 void sunxi_board_init(void)
469 int power_failed
= 0;
470 unsigned long ramsize
;
472 #ifdef CONFIG_SY8106A_POWER
473 power_failed
= sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT
);
476 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
477 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
478 defined CONFIG_AXP818_POWER
479 power_failed
= axp_init();
481 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
482 defined CONFIG_AXP818_POWER
483 power_failed
|= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT
);
485 power_failed
|= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT
);
486 power_failed
|= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT
);
487 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
488 power_failed
|= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT
);
490 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
491 defined CONFIG_AXP818_POWER
492 power_failed
|= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT
);
495 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
496 defined CONFIG_AXP818_POWER
497 power_failed
|= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT
);
499 power_failed
|= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT
);
500 #if !defined(CONFIG_AXP152_POWER)
501 power_failed
|= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT
);
503 #ifdef CONFIG_AXP209_POWER
504 power_failed
|= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT
);
507 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
508 defined(CONFIG_AXP818_POWER)
509 power_failed
|= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT
);
510 power_failed
|= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT
);
511 #if !defined CONFIG_AXP809_POWER
512 power_failed
|= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT
);
513 power_failed
|= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT
);
515 power_failed
|= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT
);
516 power_failed
|= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT
);
517 power_failed
|= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT
);
520 #ifdef CONFIG_AXP818_POWER
521 power_failed
|= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT
);
522 power_failed
|= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT
);
523 power_failed
|= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT
);
526 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
527 power_failed
|= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON
));
531 ramsize
= sunxi_dram_init();
532 printf(" %lu MiB\n", ramsize
>> 20);
537 * Only clock up the CPU to full speed if we are reasonably
538 * assured it's being powered with suitable core voltage
541 clock_set_pll1(CONFIG_SYS_CLK_FREQ
);
543 printf("Failed to set core voltage! Can't set CPU frequency\n");
547 #ifdef CONFIG_USB_GADGET
548 int g_dnl_board_usb_cable_connected(void)
550 return sunxi_usb_phy_vbus_detect(0);
554 #ifdef CONFIG_SERIAL_TAG
555 void get_board_serial(struct tag_serialnr
*serialnr
)
558 unsigned long long serial
;
560 serial_string
= getenv("serial#");
563 serial
= simple_strtoull(serial_string
, NULL
, 16);
565 serialnr
->high
= (unsigned int) (serial
>> 32);
566 serialnr
->low
= (unsigned int) (serial
& 0xffffffff);
574 #if !defined(CONFIG_SPL_BUILD)
575 #include <asm/arch/spl.h>
578 * Check the SPL header for the "sunxi" variant. If found: parse values
579 * that might have been passed by the loader ("fel" utility), and update
580 * the environment accordingly.
582 static void parse_spl_header(const uint32_t spl_addr
)
584 struct boot_file_head
*spl
= (void *)(ulong
)spl_addr
;
585 if (memcmp(spl
->spl_signature
, SPL_SIGNATURE
, 3) == 0) {
586 uint8_t spl_header_version
= spl
->spl_signature
[3];
587 if (spl_header_version
== SPL_HEADER_VERSION
) {
588 if (spl
->fel_script_address
)
589 setenv_hex("fel_scriptaddr",
590 spl
->fel_script_address
);
593 printf("sunxi SPL version mismatch: expected %u, got %u\n",
594 SPL_HEADER_VERSION
, spl_header_version
);
599 #ifdef CONFIG_MISC_INIT_R
600 int misc_init_r(void)
602 char serial_string
[17] = { 0 };
607 #if !defined(CONFIG_SPL_BUILD)
608 setenv("fel_booted", NULL
);
609 setenv("fel_scriptaddr", NULL
);
610 /* determine if we are running in FEL mode */
611 if (!is_boot0_magic(SPL_ADDR
+ 4)) { /* eGON.BT0 */
612 setenv("fel_booted", "1");
613 parse_spl_header(SPL_ADDR
);
617 ret
= sunxi_get_sid(sid
);
618 if (ret
== 0 && sid
[0] != 0 && sid
[3] != 0) {
619 if (!getenv("ethaddr")) {
620 /* Non OUI / registered MAC address */
622 mac_addr
[1] = (sid
[0] >> 0) & 0xff;
623 mac_addr
[2] = (sid
[3] >> 24) & 0xff;
624 mac_addr
[3] = (sid
[3] >> 16) & 0xff;
625 mac_addr
[4] = (sid
[3] >> 8) & 0xff;
626 mac_addr
[5] = (sid
[3] >> 0) & 0xff;
628 eth_setenv_enetaddr("ethaddr", mac_addr
);
631 if (!getenv("serial#")) {
632 snprintf(serial_string
, sizeof(serial_string
),
633 "%08x%08x", sid
[0], sid
[3]);
635 setenv("serial#", serial_string
);
639 #ifndef CONFIG_MACH_SUN9I
640 ret
= sunxi_usb_phy_probe();
644 sunxi_musb_board_init();
650 int ft_board_setup(void *blob
, bd_t
*bd
)
652 int __maybe_unused r
;
654 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
655 r
= sunxi_simplefb_setup(blob
);