board/sunxi/board.c

   1 /*
   2  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
   3  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4  *
   5  * (C) Copyright 2007-2011
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * Tom Cubie <tangliang@allwinnertech.com>
   8  *
   9  * Some board init for the Allwinner A10-evb board.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #ifdef CONFIG_AXP152_POWER
  16 #include <axp152.h>
  17 #endif
  18 #ifdef CONFIG_AXP209_POWER
  19 #include <axp209.h>
  20 #endif
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/dram.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc.h>
  26 #include <asm/io.h>
  27 #include <net.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /* add board specific code here */
  32 int board_init(void)
  33 {
  34         int id_pfr1;
  35
  36         gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  37
  38         asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  39         debug("id_pfr1: 0x%08x\n", id_pfr1);
  40         /* Generic Timer Extension available? */
  41         if ((id_pfr1 >> 16) & 0xf) {
  42                 debug("Setting CNTFRQ\n");
  43                 /* CNTFRQ == 24 MHz */
  44                 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
  45         }
  46
  47         return 0;
  48 }
  49
  50 int dram_init(void)
  51 {
  52         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
  53
  54         return 0;
  55 }
  56
  57 #ifdef CONFIG_GENERIC_MMC
  58 static void mmc_pinmux_setup(int sdc)
  59 {
  60         unsigned int pin;
  61
  62         switch (sdc) {
  63         case 0:
  64                 /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
  65                 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  66                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
  67                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  68                         sunxi_gpio_set_drv(pin, 2);
  69                 }
  70                 break;
  71
  72         case 1:
  73                 /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
  74                 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  75                         sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
  76                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  77                         sunxi_gpio_set_drv(pin, 2);
  78                 }
  79                 break;
  80
  81         case 2:
  82                 /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
  83                 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  84                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
  85                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  86                         sunxi_gpio_set_drv(pin, 2);
  87                 }
  88                 break;
  89
  90         case 3:
  91                 /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
  92                 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  93                         sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
  94                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  95                         sunxi_gpio_set_drv(pin, 2);
  96                 }
  97                 break;
  98
  99         default:
 100                 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
 101                 break;
 102         }
 103 }
 104
 105 int board_mmc_init(bd_t *bis)
 106 {
 107         mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
 108         sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
 109 #if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
 110         mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 111         sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 112 #endif
 113
 114         return 0;
 115 }
 116 #endif
 117
 118 void i2c_init_board(void)
 119 {
 120         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
 121         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
 122         clock_twi_onoff(0, 1);
 123 }
 124
 125 #ifdef CONFIG_SPL_BUILD
 126 void sunxi_board_init(void)
 127 {
 128         int power_failed = 0;
 129         unsigned long ramsize;
 130
 131 #ifdef CONFIG_AXP152_POWER
 132         power_failed = axp152_init();
 133         power_failed |= axp152_set_dcdc2(1400);
 134         power_failed |= axp152_set_dcdc3(1500);
 135         power_failed |= axp152_set_dcdc4(1250);
 136         power_failed |= axp152_set_ldo2(3000);
 137 #endif
 138 #ifdef CONFIG_AXP209_POWER
 139         power_failed |= axp209_init();
 140         power_failed |= axp209_set_dcdc2(1400);
 141         power_failed |= axp209_set_dcdc3(1250);
 142         power_failed |= axp209_set_ldo2(3000);
 143         power_failed |= axp209_set_ldo3(2800);
 144         power_failed |= axp209_set_ldo4(2800);
 145 #endif
 146
 147         printf("DRAM:");
 148         ramsize = sunxi_dram_init();
 149         printf(" %lu MiB\n", ramsize >> 20);
 150         if (!ramsize)
 151                 hang();
 152
 153         /*
 154          * Only clock up the CPU to full speed if we are reasonably
 155          * assured it's being powered with suitable core voltage
 156          */
 157         if (!power_failed)
 158                 clock_set_pll1(CONFIG_CLK_FULL_SPEED);
 159         else
 160                 printf("Failed to set core voltage! Can't set CPU frequency\n");
 161 }
 162 #endif
 163
 164 #ifdef CONFIG_MISC_INIT_R
 165 int misc_init_r(void)
 166 {
 167         if (!getenv("ethaddr")) {
 168                 uint32_t reg_val = readl(SUNXI_SID_BASE);
 169
 170                 if (reg_val) {
 171                         uint8_t mac_addr[6];
 172
 173                         mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
 174                         mac_addr[1] = (reg_val >>  0) & 0xff;
 175                         reg_val = readl(SUNXI_SID_BASE + 0x0c);
 176                         mac_addr[2] = (reg_val >> 24) & 0xff;
 177                         mac_addr[3] = (reg_val >> 16) & 0xff;
 178                         mac_addr[4] = (reg_val >>  8) & 0xff;
 179                         mac_addr[5] = (reg_val >>  0) & 0xff;
 180
 181                         eth_setenv_enetaddr("ethaddr", mac_addr);
 182                 }
 183         }
 184
 185         return 0;
 186 }
 187 #endif