board/sunxi/board.c

   1 /*
   2  * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
   3  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4  *
   5  * (C) Copyright 2007-2011
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * Tom Cubie <tangliang@allwinnertech.com>
   8  *
   9  * Some board init for the Allwinner A10-evb board.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <common.h>
  15 #include <mmc.h>
  16 #include <axp_pmic.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/display.h>
  20 #include <asm/arch/dram.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc.h>
  23 #include <asm/arch/spl.h>
  24 #include <asm/arch/usb_phy.h>
  25 #ifndef CONFIG_ARM64
  26 #include <asm/armv7.h>
  27 #endif
  28 #include <asm/gpio.h>
  29 #include <asm/io.h>
  30 #include <crc.h>
  31 #include <environment.h>
  32 #include <libfdt.h>
  33 #include <nand.h>
  34 #include <net.h>
  35 #include <spl.h>
  36 #include <sy8106a.h>
  37 #include <asm/setup.h>
  38
  39 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
  40 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
  41 int soft_i2c_gpio_sda;
  42 int soft_i2c_gpio_scl;
  43
  44 static int soft_i2c_board_init(void)
  45 {
  46         int ret;
  47
  48         soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
  49         if (soft_i2c_gpio_sda < 0) {
  50                 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
  51                        CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
  52                 return soft_i2c_gpio_sda;
  53         }
  54         ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
  55         if (ret) {
  56                 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
  57                        CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
  58                 return ret;
  59         }
  60
  61         soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
  62         if (soft_i2c_gpio_scl < 0) {
  63                 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
  64                        CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
  65                 return soft_i2c_gpio_scl;
  66         }
  67         ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
  68         if (ret) {
  69                 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
  70                        CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
  71                 return ret;
  72         }
  73
  74         return 0;
  75 }
  76 #else
  77 static int soft_i2c_board_init(void) { return 0; }
  78 #endif
  79
  80 DECLARE_GLOBAL_DATA_PTR;
  81
  82 void i2c_init_board(void)
  83 {
  84 #ifdef CONFIG_I2C0_ENABLE
  85 #if defined(CONFIG_MACH_SUN4I) || \
  86     defined(CONFIG_MACH_SUN5I) || \
  87     defined(CONFIG_MACH_SUN7I) || \
  88     defined(CONFIG_MACH_SUN8I_R40)
  89         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  90         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
  91         clock_twi_onoff(0, 1);
  92 #elif defined(CONFIG_MACH_SUN6I)
  93         sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  94         sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  95         clock_twi_onoff(0, 1);
  96 #elif defined(CONFIG_MACH_SUN8I)
  97         sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  98         sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  99         clock_twi_onoff(0, 1);
 100 #endif
 101 #endif
 102
 103 #ifdef CONFIG_I2C1_ENABLE
 104 #if defined(CONFIG_MACH_SUN4I) || \
 105     defined(CONFIG_MACH_SUN7I) || \
 106     defined(CONFIG_MACH_SUN8I_R40)
 107         sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
 108         sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
 109         clock_twi_onoff(1, 1);
 110 #elif defined(CONFIG_MACH_SUN5I)
 111         sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
 112         sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
 113         clock_twi_onoff(1, 1);
 114 #elif defined(CONFIG_MACH_SUN6I)
 115         sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
 116         sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
 117         clock_twi_onoff(1, 1);
 118 #elif defined(CONFIG_MACH_SUN8I)
 119         sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
 120         sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
 121         clock_twi_onoff(1, 1);
 122 #endif
 123 #endif
 124
 125 #ifdef CONFIG_I2C2_ENABLE
 126 #if defined(CONFIG_MACH_SUN4I) || \
 127     defined(CONFIG_MACH_SUN7I) || \
 128     defined(CONFIG_MACH_SUN8I_R40)
 129         sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
 130         sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
 131         clock_twi_onoff(2, 1);
 132 #elif defined(CONFIG_MACH_SUN5I)
 133         sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
 134         sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
 135         clock_twi_onoff(2, 1);
 136 #elif defined(CONFIG_MACH_SUN6I)
 137         sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
 138         sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
 139         clock_twi_onoff(2, 1);
 140 #elif defined(CONFIG_MACH_SUN8I)
 141         sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
 142         sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
 143         clock_twi_onoff(2, 1);
 144 #endif
 145 #endif
 146
 147 #ifdef CONFIG_I2C3_ENABLE
 148 #if defined(CONFIG_MACH_SUN6I)
 149         sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
 150         sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
 151         clock_twi_onoff(3, 1);
 152 #elif defined(CONFIG_MACH_SUN7I) || \
 153       defined(CONFIG_MACH_SUN8I_R40)
 154         sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
 155         sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
 156         clock_twi_onoff(3, 1);
 157 #endif
 158 #endif
 159
 160 #ifdef CONFIG_I2C4_ENABLE
 161 #if defined(CONFIG_MACH_SUN7I) || \
 162     defined(CONFIG_MACH_SUN8I_R40)
 163         sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
 164         sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
 165         clock_twi_onoff(4, 1);
 166 #endif
 167 #endif
 168
 169 #ifdef CONFIG_R_I2C_ENABLE
 170         clock_twi_onoff(5, 1);
 171         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
 172         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
 173 #endif
 174 }
 175
 176 /* add board specific code here */
 177 int board_init(void)
 178 {
 179         __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
 180
 181         gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
 182
 183 #ifndef CONFIG_ARM64
 184         asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
 185         debug("id_pfr1: 0x%08x\n", id_pfr1);
 186         /* Generic Timer Extension available? */
 187         if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
 188                 uint32_t freq;
 189
 190                 debug("Setting CNTFRQ\n");
 191
 192                 /*
 193                  * CNTFRQ is a secure register, so we will crash if we try to
 194                  * write this from the non-secure world (read is OK, though).
 195                  * In case some bootcode has already set the correct value,
 196                  * we avoid the risk of writing to it.
 197                  */
 198                 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
 199                 if (freq != COUNTER_FREQUENCY) {
 200                         debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
 201                               freq, COUNTER_FREQUENCY);
 202 #ifdef CONFIG_NON_SECURE
 203                         printf("arch timer frequency is wrong, but cannot adjust it\n");
 204 #else
 205                         asm volatile("mcr p15, 0, %0, c14, c0, 0"
 206                                      : : "r"(COUNTER_FREQUENCY));
 207 #endif
 208                 }
 209         }
 210 #endif /* !CONFIG_ARM64 */
 211
 212         ret = axp_gpio_init();
 213         if (ret)
 214                 return ret;
 215
 216 #ifdef CONFIG_SATAPWR
 217         satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
 218         gpio_request(satapwr_pin, "satapwr");
 219         gpio_direction_output(satapwr_pin, 1);
 220 #endif
 221 #ifdef CONFIG_MACPWR
 222         macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
 223         gpio_request(macpwr_pin, "macpwr");
 224         gpio_direction_output(macpwr_pin, 1);
 225 #endif
 226
 227 #ifdef CONFIG_DM_I2C
 228         /*
 229          * Temporary workaround for enabling I2C clocks until proper sunxi DM
 230          * clk, reset and pinctrl drivers land.
 231          */
 232         i2c_init_board();
 233 #endif
 234
 235         /* Uses dm gpio code so do this here and not in i2c_init_board() */
 236         return soft_i2c_board_init();
 237 }
 238
 239 int dram_init(void)
 240 {
 241         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
 242
 243         return 0;
 244 }
 245
 246 #if defined(CONFIG_NAND_SUNXI)
 247 static void nand_pinmux_setup(void)
 248 {
 249         unsigned int pin;
 250
 251         for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
 252                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
 253
 254 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
 255         for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
 256                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
 257 #endif
 258         /* sun4i / sun7i do have a PC23, but it is not used for nand,
 259          * only sun7i has a PC24 */
 260 #ifdef CONFIG_MACH_SUN7I
 261         sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
 262 #endif
 263 }
 264
 265 static void nand_clock_setup(void)
 266 {
 267         struct sunxi_ccm_reg *const ccm =
 268                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 269
 270         setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
 271 #ifdef CONFIG_MACH_SUN9I
 272         setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 273 #else
 274         setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
 275 #endif
 276         setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
 277 }
 278
 279 void board_nand_init(void)
 280 {
 281         nand_pinmux_setup();
 282         nand_clock_setup();
 283 #ifndef CONFIG_SPL_BUILD
 284         sunxi_nand_init();
 285 #endif
 286 }
 287 #endif
 288
 289 #ifdef CONFIG_MMC
 290 static void mmc_pinmux_setup(int sdc)
 291 {
 292         unsigned int pin;
 293         __maybe_unused int pins;
 294
 295         switch (sdc) {
 296         case 0:
 297                 /* SDC0: PF0-PF5 */
 298                 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
 299                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
 300                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 301                         sunxi_gpio_set_drv(pin, 2);
 302                 }
 303                 break;
 304
 305         case 1:
 306                 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
 307
 308 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
 309     defined(CONFIG_MACH_SUN8I_R40)
 310                 if (pins == SUNXI_GPIO_H) {
 311                         /* SDC1: PH22-PH-27 */
 312                         for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
 313                                 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
 314                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 315                                 sunxi_gpio_set_drv(pin, 2);
 316                         }
 317                 } else {
 318                         /* SDC1: PG0-PG5 */
 319                         for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
 320                                 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
 321                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 322                                 sunxi_gpio_set_drv(pin, 2);
 323                         }
 324                 }
 325 #elif defined(CONFIG_MACH_SUN5I)
 326                 /* SDC1: PG3-PG8 */
 327                 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
 328                         sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
 329                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 330                         sunxi_gpio_set_drv(pin, 2);
 331                 }
 332 #elif defined(CONFIG_MACH_SUN6I)
 333                 /* SDC1: PG0-PG5 */
 334                 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
 335                         sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
 336                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 337                         sunxi_gpio_set_drv(pin, 2);
 338                 }
 339 #elif defined(CONFIG_MACH_SUN8I)
 340                 if (pins == SUNXI_GPIO_D) {
 341                         /* SDC1: PD2-PD7 */
 342                         for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
 343                                 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
 344                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 345                                 sunxi_gpio_set_drv(pin, 2);
 346                         }
 347                 } else {
 348                         /* SDC1: PG0-PG5 */
 349                         for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
 350                                 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
 351                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 352                                 sunxi_gpio_set_drv(pin, 2);
 353                         }
 354                 }
 355 #endif
 356                 break;
 357
 358         case 2:
 359                 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
 360
 361 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
 362                 /* SDC2: PC6-PC11 */
 363                 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
 364                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 365                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 366                         sunxi_gpio_set_drv(pin, 2);
 367                 }
 368 #elif defined(CONFIG_MACH_SUN5I)
 369                 if (pins == SUNXI_GPIO_E) {
 370                         /* SDC2: PE4-PE9 */
 371                         for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
 372                                 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
 373                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 374                                 sunxi_gpio_set_drv(pin, 2);
 375                         }
 376                 } else {
 377                         /* SDC2: PC6-PC15 */
 378                         for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 379                                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 380                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 381                                 sunxi_gpio_set_drv(pin, 2);
 382                         }
 383                 }
 384 #elif defined(CONFIG_MACH_SUN6I)
 385                 if (pins == SUNXI_GPIO_A) {
 386                         /* SDC2: PA9-PA14 */
 387                         for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
 388                                 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
 389                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 390                                 sunxi_gpio_set_drv(pin, 2);
 391                         }
 392                 } else {
 393                         /* SDC2: PC6-PC15, PC24 */
 394                         for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 395                                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 396                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 397                                 sunxi_gpio_set_drv(pin, 2);
 398                         }
 399
 400                         sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
 401                         sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 402                         sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 403                 }
 404 #elif defined(CONFIG_MACH_SUN8I_R40)
 405                 /* SDC2: PC6-PC15, PC24 */
 406                 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 407                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 408                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 409                         sunxi_gpio_set_drv(pin, 2);
 410                 }
 411
 412                 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
 413                 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 414                 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 415 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
 416                 /* SDC2: PC5-PC6, PC8-PC16 */
 417                 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
 418                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 419                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 420                         sunxi_gpio_set_drv(pin, 2);
 421                 }
 422
 423                 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
 424                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 425                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 426                         sunxi_gpio_set_drv(pin, 2);
 427                 }
 428 #elif defined(CONFIG_MACH_SUN9I)
 429                 /* SDC2: PC6-PC16 */
 430                 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
 431                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
 432                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 433                         sunxi_gpio_set_drv(pin, 2);
 434                 }
 435 #endif
 436                 break;
 437
 438         case 3:
 439                 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
 440
 441 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
 442     defined(CONFIG_MACH_SUN8I_R40)
 443                 /* SDC3: PI4-PI9 */
 444                 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
 445                         sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
 446                         sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 447                         sunxi_gpio_set_drv(pin, 2);
 448                 }
 449 #elif defined(CONFIG_MACH_SUN6I)
 450                 if (pins == SUNXI_GPIO_A) {
 451                         /* SDC3: PA9-PA14 */
 452                         for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
 453                                 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
 454                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 455                                 sunxi_gpio_set_drv(pin, 2);
 456                         }
 457                 } else {
 458                         /* SDC3: PC6-PC15, PC24 */
 459                         for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
 460                                 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
 461                                 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 462                                 sunxi_gpio_set_drv(pin, 2);
 463                         }
 464
 465                         sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
 466                         sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 467                         sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 468                 }
 469 #endif
 470                 break;
 471
 472         default:
 473                 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
 474                 break;
 475         }
 476 }
 477
 478 int board_mmc_init(bd_t *bis)
 479 {
 480         __maybe_unused struct mmc *mmc0, *mmc1;
 481         __maybe_unused char buf[512];
 482
 483         mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
 484         mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
 485         if (!mmc0)
 486                 return -1;
 487
 488 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
 489         mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 490         mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
 491         if (!mmc1)
 492                 return -1;
 493 #endif
 494
 495         return 0;
 496 }
 497 #endif
 498
 499 #ifdef CONFIG_SPL_BUILD
 500 void sunxi_board_init(void)
 501 {
 502         int power_failed = 0;
 503
 504 #ifdef CONFIG_SY8106A_POWER
 505         power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
 506 #endif
 507
 508 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
 509         defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
 510         defined CONFIG_AXP818_POWER
 511         power_failed = axp_init();
 512
 513 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
 514         defined CONFIG_AXP818_POWER
 515         power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 516 #endif
 517         power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
 518         power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
 519 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
 520         power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
 521 #endif
 522 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
 523         defined CONFIG_AXP818_POWER
 524         power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
 525 #endif
 526
 527 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
 528         defined CONFIG_AXP818_POWER
 529         power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
 530 #endif
 531         power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
 532 #if !defined(CONFIG_AXP152_POWER)
 533         power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
 534 #endif
 535 #ifdef CONFIG_AXP209_POWER
 536         power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
 537 #endif
 538
 539 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
 540         defined(CONFIG_AXP818_POWER)
 541         power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
 542         power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
 543 #if !defined CONFIG_AXP809_POWER
 544         power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
 545         power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
 546 #endif
 547         power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
 548         power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
 549         power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
 550 #endif
 551
 552 #ifdef CONFIG_AXP818_POWER
 553         power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
 554         power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
 555         power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
 556 #endif
 557
 558 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 559         power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
 560 #endif
 561 #endif
 562         printf("DRAM:");
 563         gd->ram_size = sunxi_dram_init();
 564         printf(" %d MiB\n", (int)(gd->ram_size >> 20));
 565         if (!gd->ram_size)
 566                 hang();
 567
 568         /*
 569          * Only clock up the CPU to full speed if we are reasonably
 570          * assured it's being powered with suitable core voltage
 571          */
 572         if (!power_failed)
 573                 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
 574         else
 575                 printf("Failed to set core voltage! Can't set CPU frequency\n");
 576 }
 577 #endif
 578
 579 #ifdef CONFIG_USB_GADGET
 580 int g_dnl_board_usb_cable_connected(void)
 581 {
 582         return sunxi_usb_phy_vbus_detect(0);
 583 }
 584 #endif
 585
 586 #ifdef CONFIG_SERIAL_TAG
 587 void get_board_serial(struct tag_serialnr *serialnr)
 588 {
 589         char *serial_string;
 590         unsigned long long serial;
 591
 592         serial_string = env_get("serial#");
 593
 594         if (serial_string) {
 595                 serial = simple_strtoull(serial_string, NULL, 16);
 596
 597                 serialnr->high = (unsigned int) (serial >> 32);
 598                 serialnr->low = (unsigned int) (serial & 0xffffffff);
 599         } else {
 600                 serialnr->high = 0;
 601                 serialnr->low = 0;
 602         }
 603 }
 604 #endif
 605
 606 /*
 607  * Check the SPL header for the "sunxi" variant. If found: parse values
 608  * that might have been passed by the loader ("fel" utility), and update
 609  * the environment accordingly.
 610  */
 611 static void parse_spl_header(const uint32_t spl_addr)
 612 {
 613         struct boot_file_head *spl = (void *)(ulong)spl_addr;
 614         if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
 615                 return; /* signature mismatch, no usable header */
 616
 617         uint8_t spl_header_version = spl->spl_signature[3];
 618         if (spl_header_version != SPL_HEADER_VERSION) {
 619                 printf("sunxi SPL version mismatch: expected %u, got %u\n",
 620                        SPL_HEADER_VERSION, spl_header_version);
 621                 return;
 622         }
 623         if (!spl->fel_script_address)
 624                 return;
 625
 626         if (spl->fel_uEnv_length != 0) {
 627                 /*
 628                  * data is expected in uEnv.txt compatible format, so "env
 629                  * import -t" the string(s) at fel_script_address right away.
 630                  */
 631                 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
 632                           spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
 633                 return;
 634         }
 635         /* otherwise assume .scr format (mkimage-type script) */
 636         env_set_hex("fel_scriptaddr", spl->fel_script_address);
 637 }
 638
 639 /*
 640  * Note this function gets called multiple times.
 641  * It must not make any changes to env variables which already exist.
 642  */
 643 static void setup_environment(const void *fdt)
 644 {
 645         char serial_string[17] = { 0 };
 646         unsigned int sid[4];
 647         uint8_t mac_addr[6];
 648         char ethaddr[16];
 649         int i, ret;
 650
 651         ret = sunxi_get_sid(sid);
 652         if (ret == 0 && sid[0] != 0) {
 653                 /*
 654                  * The single words 1 - 3 of the SID have quite a few bits
 655                  * which are the same on many models, so we take a crc32
 656                  * of all 3 words, to get a more unique value.
 657                  *
 658                  * Note we only do this on newer SoCs as we cannot change
 659                  * the algorithm on older SoCs since those have been using
 660                  * fixed mac-addresses based on only using word 3 for a
 661                  * long time and changing a fixed mac-address with an
 662                  * u-boot update is not good.
 663                  */
 664 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
 665     !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
 666     !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
 667                 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
 668 #endif
 669
 670                 /* Ensure the NIC specific bytes of the mac are not all 0 */
 671                 if ((sid[3] & 0xffffff) == 0)
 672                         sid[3] |= 0x800000;
 673
 674                 for (i = 0; i < 4; i++) {
 675                         sprintf(ethaddr, "ethernet%d", i);
 676                         if (!fdt_get_alias(fdt, ethaddr))
 677                                 continue;
 678
 679                         if (i == 0)
 680                                 strcpy(ethaddr, "ethaddr");
 681                         else
 682                                 sprintf(ethaddr, "eth%daddr", i);
 683
 684                         if (env_get(ethaddr))
 685                                 continue;
 686
 687                         /* Non OUI / registered MAC address */
 688                         mac_addr[0] = (i << 4) | 0x02;
 689                         mac_addr[1] = (sid[0] >>  0) & 0xff;
 690                         mac_addr[2] = (sid[3] >> 24) & 0xff;
 691                         mac_addr[3] = (sid[3] >> 16) & 0xff;
 692                         mac_addr[4] = (sid[3] >>  8) & 0xff;
 693                         mac_addr[5] = (sid[3] >>  0) & 0xff;
 694
 695                         eth_env_set_enetaddr(ethaddr, mac_addr);
 696                 }
 697
 698                 if (!env_get("serial#")) {
 699                         snprintf(serial_string, sizeof(serial_string),
 700                                 "%08x%08x", sid[0], sid[3]);
 701
 702                         env_set("serial#", serial_string);
 703                 }
 704         }
 705 }
 706
 707 int misc_init_r(void)
 708 {
 709         __maybe_unused int ret;
 710         uint boot;
 711
 712         env_set("fel_booted", NULL);
 713         env_set("fel_scriptaddr", NULL);
 714         env_set("mmc_bootdev", NULL);
 715
 716         boot = sunxi_get_boot_device();
 717         /* determine if we are running in FEL mode */
 718         if (boot == BOOT_DEVICE_BOARD) {
 719                 env_set("fel_booted", "1");
 720                 parse_spl_header(SPL_ADDR);
 721         /* or if we booted from MMC, and which one */
 722         } else if (boot == BOOT_DEVICE_MMC1) {
 723                 env_set("mmc_bootdev", "0");
 724         } else if (boot == BOOT_DEVICE_MMC2) {
 725                 env_set("mmc_bootdev", "1");
 726         }
 727
 728         setup_environment(gd->fdt_blob);
 729
 730 #ifndef CONFIG_MACH_SUN9I
 731         ret = sunxi_usb_phy_probe();
 732         if (ret)
 733                 return ret;
 734 #endif
 735
 736 #ifdef CONFIG_USB_ETHER
 737         usb_ether_init();
 738 #endif
 739
 740         return 0;
 741 }
 742
 743 int ft_board_setup(void *blob, bd_t *bd)
 744 {
 745         int __maybe_unused r;
 746
 747         /*
 748          * Call setup_environment again in case the boot fdt has
 749          * ethernet aliases the u-boot copy does not have.
 750          */
 751         setup_environment(blob);
 752
 753 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
 754         r = sunxi_simplefb_setup(blob);
 755         if (r)
 756                 return r;
 757 #endif
 758         return 0;
 759 }
 760
 761 #ifdef CONFIG_SPL_LOAD_FIT
 762 int board_fit_config_name_match(const char *name)
 763 {
 764         struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
 765         const char *cmp_str = (void *)(ulong)SPL_ADDR;
 766
 767         /* Check if there is a DT name stored in the SPL header and use that. */
 768         if (spl->dt_name_offset) {
 769                 cmp_str += spl->dt_name_offset;
 770         } else {
 771 #ifdef CONFIG_DEFAULT_DEVICE_TREE
 772                 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
 773 #else
 774                 return 0;
 775 #endif
 776         };
 777
 778 /* Differentiate the two Pine64 board DTs by their DRAM size. */
 779         if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
 780                 if ((gd->ram_size > 512 * 1024 * 1024))
 781                         return !strstr(name, "plus");
 782                 else
 783                         return !!strstr(name, "plus");
 784         } else {
 785                 return strcmp(name, cmp_str);
 786         }
 787 }
 788 #endif