board/sysam/amcore/amcore.c

   1 /*
   2  * Board functions for Sysam AMCORE (MCF5307 based) board
   3  *
   4  * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  *
   8  * This file copies memory testdram() from sandburst/common/sb_common.c
   9  */
  10
  11 #include <common.h>
  12 #include <asm/immap.h>
  13 #include <asm/io.h>
  14 #include <dm.h>
  15 #include <dm/platform_data/serial_coldfire.h>
  16
  17 void init_lcd(void)
  18 {
  19         /* setup for possible K0108 lcd connected on the parallel port */
  20         sim_t *sim = (sim_t *)(MMAP_SIM);
  21
  22         out_be16(&sim->par, 0x300);
  23
  24         gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
  25
  26         out_be16(&gpio->paddr, 0xfcff);
  27         out_be16(&gpio->padat, 0x0c00);
  28 }
  29
  30 int checkboard(void)
  31 {
  32         puts("Board: ");
  33         puts("AMCORE v.001(alpha)\n");
  34
  35         init_lcd();
  36
  37         return 0;
  38 }
  39
  40 /*
  41  * in initdram we are here executing from flash
  42  * case 1:
  43  * is with no ACR/flash cache enabled
  44  * nop = 40ns (scope measured)
  45  */
  46 void fudelay(int usec)
  47 {
  48         while (usec--)
  49                 asm volatile ("nop");
  50 }
  51
  52 phys_size_t initdram(int board_type)
  53 {
  54         u32 dramsize, RC;
  55
  56         sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
  57
  58         /*
  59          * SDRAM  MT48LC4M32B2 details
  60          * Memory block 0: 16 MB of SDRAM at address $00000000
  61          * Port size: 32-bit port
  62          *
  63          * Memory block 0 wired as follows:
  64          * CPU   : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
  65          * SDRAM :  A0  A1  A2  A3  A4  A5  A6 A7  A8  A9 A10 A11 BA0 BA1
  66          *
  67          * Ensure that there is a delay of at least 100 microseconds from
  68          * processor reset to the following code so that the SDRAM is ready
  69          * for commands.
  70          */
  71         fudelay(100);
  72
  73         /*
  74          * DCR
  75          * set proper  RC as per specification
  76          */
  77         RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
  78         RC = (RC * 15) >> 4;
  79
  80         /* 0x8000 is the faster option */
  81         out_be16(&dc->dcr, 0x8200 | RC);
  82
  83         /*
  84          * DACR0, page mode continuous, CMD on A20 0x0300
  85          */
  86         out_be32(&dc->dacr0, 0x00003304);
  87
  88         dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
  89         out_be32(&dc->dmr0,  dramsize|1);
  90
  91         /* issue a PRECHARGE ALL */
  92         out_be32(&dc->dacr0, 0x0000330c);
  93         out_be32((u32 *)0x00000004, 0xbeaddeed);
  94         /* issue AUTOREFRESH */
  95         out_be32(&dc->dacr0, 0x0000b304);
  96         /* let refresh occour */
  97         fudelay(1);
  98
  99         out_be32(&dc->dacr0, 0x0000b344);
 100         out_be32((u32 *)0x00000c00, 0xbeaddeed);
 101
 102         return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
 103 }
 104
 105 static struct coldfire_serial_platdata mcf5307_serial_plat = {
 106         .base = CONFIG_SYS_UART_BASE,
 107         .port = 0,
 108         .baudrate = CONFIG_BAUDRATE,
 109 };
 110
 111 U_BOOT_DEVICE(coldfire_serial) = {
 112         .name = "serial_coldfire",
 113         .platdata = &mcf5307_serial_plat,
 114 };