board/syteco/zmx25/lowlevel_init.S

   1 /*
   2  * (C) Copyright 2011
   3  * Matthias Weisser <weisserm@arcor.de>
   4  *
   5  * (C) Copyright 2009 DENX Software Engineering
   6  * Author: John Rigby <jrigby@gmail.com>
   7  *
   8  * Based on U-Boot and RedBoot sources for several different i.mx
   9  * platforms.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <asm/macro.h>
  28 #include <asm/arch/macro.h>
  29 #include <asm/arch/imx-regs.h>
  30 #include <asm/arch/asm-offsets.h>
  31
  32 /*
  33  * clocks
  34  */
  35 .macro init_clocks
  36
  37         /* disable clock output */
  38         write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
  39         write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
  40
  41         /*
  42          * enable all implemented clocks in all three
  43          * clock control registers
  44          */
  45         write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
  46         write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
  47         write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
  48
  49         /* Devide NAND clock by 32 */
  50         write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
  51 .endm
  52
  53 /*
  54  * sdram controller init
  55  */
  56 .macro init_lpddr
  57         ldr     r0, =IMX_ESDRAMC_BASE
  58         ldr     r2, =IMX_SDRAM_BANK0_BASE
  59
  60         /*
  61          * reset SDRAM controller
  62          * then wait for initialization to complete
  63          */
  64         ldr     r1, =(1 << 1) | (1 << 2)
  65         str     r1, [r0, #ESDRAMC_ESDMISC]
  66 1:      ldr     r3, [r0, #ESDRAMC_ESDMISC]
  67         tst     r3, #(1 << 31)
  68         beq     1b
  69         ldr     r1, =(1 << 2)
  70         str     r1, [r0, #ESDRAMC_ESDMISC]
  71
  72         ldr     r1, =0x002a7420
  73         str     r1, [r0, #ESDRAMC_ESDCFG0]
  74
  75         /* control | precharge */
  76         ldr     r1, =0x92216008
  77         str     r1, [r0, #ESDRAMC_ESDCTL0]
  78         /* dram command encoded in address */
  79         str     r1, [r2, #0x400]
  80
  81         /* auto refresh */
  82         ldr     r1, =0xa2216008
  83         str     r1, [r0, #ESDRAMC_ESDCTL0]
  84         /* read dram twice to auto refresh */
  85         ldr         r3, [r2]
  86         ldr     r3, [r2]
  87
  88         /* control | load mode */
  89         ldr     r1, =0xb2216008
  90         str     r1, [r0, #ESDRAMC_ESDCTL0]
  91
  92         /* mode register of lpddram */
  93         strb    r1, [r2, #0x33]
  94
  95         /* extended mode register of lpddrram */
  96         ldr             r2, =0x81000000
  97         strb    r1, [r2]
  98
  99         /* control | normal */
 100         ldr     r1, =0x82216008
 101         str     r1, [r0, #ESDRAMC_ESDCTL0]
 102 .endm
 103
 104 .globl lowlevel_init
 105 lowlevel_init:
 106         init_aips
 107         init_max
 108         init_clocks
 109         init_lpddr
 110         mov     pc, lr