]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/t3corp/t3corp.c
f2853e42e58c4636b9728092f062de33a62b9667
[people/ms/u-boot.git] / board / t3corp / t3corp.c
1 /*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 #include <common.h>
22 #include <asm/ppc440.h>
23 #include <libfdt.h>
24 #include <fdt_support.h>
25 #include <i2c.h>
26 #include <mtd/cfi_flash.h>
27 #include <asm/processor.h>
28 #include <asm/io.h>
29 #include <asm/mmu.h>
30 #include <asm/4xx_pcie.h>
31 #include <asm/ppc4xx-gpio.h>
32
33 int board_early_init_f(void)
34 {
35 /*
36 * Setup the interrupt controller polarities, triggers, etc.
37 */
38 mtdcr(UIC0SR, 0xffffffff); /* clear all */
39 mtdcr(UIC0ER, 0x00000000); /* disable all */
40 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
41 mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
42 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
43 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
44 mtdcr(UIC0SR, 0xffffffff); /* clear all */
45
46 mtdcr(UIC1SR, 0xffffffff); /* clear all */
47 mtdcr(UIC1ER, 0x00000000); /* disable all */
48 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
49 mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
50 mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
51 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
52 mtdcr(UIC1SR, 0xffffffff); /* clear all */
53
54 mtdcr(UIC2SR, 0xffffffff); /* clear all */
55 mtdcr(UIC2ER, 0x00000000); /* disable all */
56 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
57 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
58 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
59 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
60 mtdcr(UIC2SR, 0xffffffff); /* clear all */
61
62 mtdcr(UIC3SR, 0xffffffff); /* clear all */
63 mtdcr(UIC3ER, 0x00000000); /* disable all */
64 mtdcr(UIC3CR, 0x00000000); /* all non-critical */
65 mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
66 mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
67 mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
68 mtdcr(UIC3SR, 0xffffffff); /* clear all */
69
70 /*
71 * Configure PFC (Pin Function Control) registers
72 * enable GPIO 49-63
73 * UART0: 4 pins
74 */
75 mtsdr(SDR0_PFC0, 0x00007fff);
76 mtsdr(SDR0_PFC1, 0x00040000);
77
78 /* Enable PCI host functionality in SDR0_PCI0 */
79 mtsdr(SDR0_PCI0, 0xe0000000);
80
81 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
82
83 /* Setup PLB4-AHB bridge based on the system address map */
84 mtdcr(AHB_TOP, 0x8000004B);
85 mtdcr(AHB_BOT, 0x8000004B);
86
87 return 0;
88 }
89
90 int checkboard(void)
91 {
92 char *s = getenv("serial#");
93
94 printf("Board: T3CORP");
95
96 if (s != NULL) {
97 puts(", serial# ");
98 puts(s);
99 }
100 putc('\n');
101
102 return 0;
103 }
104
105 int board_early_init_r(void)
106 {
107 /*
108 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
109 * boot EBC mapping only supports a maximum of 16MBytes
110 * (4.ff00.0000 - 4.ffff.ffff).
111 * To solve this problem, the flash has to get remapped to another
112 * EBC address which accepts bigger regions:
113 *
114 * 0xfn00.0000 -> 4.cn00.0000
115 */
116
117 /* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
118 mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
119 EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
120
121 /* Remove TLB entry of boot EBC mapping */
122 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
123
124 /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
125 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
126 CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
127
128 /*
129 * Now accessing of the whole 64Mbytes of NOR flash at virtual address
130 * 0xfc00.0000 is possible
131 */
132
133 /*
134 * Clear potential errors resulting from auto-calibration.
135 * If not done, then we could get an interrupt later on when
136 * exceptions are enabled.
137 */
138 set_mcsr(get_mcsr());
139
140 return 0;
141 }
142
143 int misc_init_r(void)
144 {
145 u32 sdr0_srst1 = 0;
146 u32 eth_cfg;
147
148 /*
149 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
150 * This is board specific, so let's do it here.
151 */
152 mfsdr(SDR0_ETH_CFG, eth_cfg);
153 /* disable SGMII mode */
154 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
155 SDR0_ETH_CFG_SGMII1_ENABLE |
156 SDR0_ETH_CFG_SGMII0_ENABLE);
157 /* Set the for 2 RGMII mode */
158 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
159 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
160 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
161 mtsdr(SDR0_ETH_CFG, eth_cfg);
162
163 /*
164 * The AHB Bridge core is held in reset after power-on or reset
165 * so enable it now
166 */
167 mfsdr(SDR0_SRST1, sdr0_srst1);
168 sdr0_srst1 &= ~SDR0_SRST1_AHB;
169 mtsdr(SDR0_SRST1, sdr0_srst1);
170
171 return 0;
172 }
173
174 int board_pcie_last(void)
175 {
176 /*
177 * Only PCIe0 for now, PCIe1 hangs on this board
178 */
179 return 0;
180 }
181
182 /*
183 * Board specific WRDTR and CLKTR values used by the auto-
184 * calibration code (4xx_ibm_ddr2_autocalib.c).
185 */
186 static struct sdram_timing board_scan_options[] = {
187 {1, 2},
188 {-1, -1}
189 };
190
191 struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
192 {
193 return board_scan_options;
194 }
195
196 /*
197 * Accessor functions replacing the "weak" functions in
198 * drivers/mtd/cfi_flash.c
199 *
200 * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
201 * can only be read correctly in 16bit mode. We need to emulate
202 * 8bit and 32bit reads here in the board specific code.
203 */
204 u8 flash_read8(void *addr)
205 {
206 u16 val = __raw_readw((void *)((u32)addr & ~1));
207
208 if ((u32)addr & 1)
209 return val;
210
211 return val >> 8;
212 }
213
214 u32 flash_read32(void *addr)
215 {
216 return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
217 }
218
219 void flash_cmd_reset(flash_info_t *info)
220 {
221 /*
222 * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
223 * needs the Spansion type reset commands. The other flash chip
224 * is located behind a FPGA (Xilinx DS617) and needs the Intel type
225 * reset command.
226 */
227 if (info->start[0] == CONFIG_SYS_FLASH_BASE)
228 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
229 else
230 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
231 }