board/tbs/tbs2910/tbs2910.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
   4  */
   5
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/imx-regs.h>
   8 #include <asm/arch/iomux.h>
   9 #include <asm/arch/mx6-pins.h>
  10 #include <linux/errno.h>
  11 #include <asm/gpio.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/mach-imx/sata.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <asm/mach-imx/video.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <miiphy.h>
  19 #include <netdev.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/sys_proto.h>
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define WEAK_PULLUP     (PAD_CTL_PUS_47K_UP |                   \
  27         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  28         PAD_CTL_SRE_SLOW)
  29
  30 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  31         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  32         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  33
  34 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  35         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  40
  41 static iomux_v3_cfg_t const uart1_pads[] = {
  42         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  43         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  44 };
  45
  46 static iomux_v3_cfg_t const uart2_pads[] = {
  47         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  48         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  49 };
  50
  51 static iomux_v3_cfg_t const enet_pads[] = {
  52         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  53         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  56         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         /* AR8035 PHY Reset */
  68         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  69 };
  70
  71 static iomux_v3_cfg_t const pcie_pads[] = {
  72         /* W_DISABLE# */
  73         MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
  74         /* PERST# */
  75         MX6_PAD_GPIO_17__GPIO7_IO12  | MUX_PAD_CTRL(NO_PAD_CTRL),
  76 };
  77
  78 int dram_init(void)
  79 {
  80         gd->ram_size = 2048ul * 1024 * 1024;
  81         return 0;
  82 }
  83
  84 static void setup_iomux_enet(void)
  85 {
  86         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  87
  88         /* Reset AR8035 PHY */
  89         gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
  90         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  91         udelay(500);
  92         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  93 }
  94
  95 static void setup_pcie(void)
  96 {
  97         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  98 }
  99
 100 static void setup_iomux_uart(void)
 101 {
 102         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 103         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 104 }
 105
 106 #ifdef CONFIG_FSL_ESDHC
 107 static iomux_v3_cfg_t const usdhc2_pads[] = {
 108         MX6_PAD_SD2_CLK__SD2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_SD2_CMD__SD2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 110         MX6_PAD_SD2_DAT0__SD2_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 111         MX6_PAD_SD2_DAT1__SD2_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_SD2_DAT2__SD2_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_DAT3__SD2_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 115 };
 116
 117 static iomux_v3_cfg_t const usdhc3_pads[] = {
 118         MX6_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD3_DAT0__SD3_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_SD3_DAT1__SD3_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 122         MX6_PAD_SD3_DAT2__SD3_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_DAT3__SD3_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 125 };
 126
 127 static iomux_v3_cfg_t const usdhc4_pads[] = {
 128         MX6_PAD_SD4_CLK__SD4_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD4_CMD__SD4_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138 };
 139
 140 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 141         {USDHC2_BASE_ADDR},
 142         {USDHC3_BASE_ADDR},
 143         {USDHC4_BASE_ADDR},
 144 };
 145
 146 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 147 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 148
 149 int board_mmc_getcd(struct mmc *mmc)
 150 {
 151         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 152         int ret = 0;
 153
 154         switch (cfg->esdhc_base) {
 155         case USDHC2_BASE_ADDR:
 156                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 157                 break;
 158         case USDHC3_BASE_ADDR:
 159                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 160                 break;
 161         case USDHC4_BASE_ADDR:
 162                 ret = 1; /* eMMC/uSDHC4 is always present */
 163                 break;
 164         }
 165         return ret;
 166 }
 167
 168 int board_mmc_init(bd_t *bis)
 169 {
 170         /*
 171          * (U-Boot device node)    (Physical Port)
 172          * mmc0                    SD2
 173          * mmc1                    SD3
 174          * mmc2                    eMMC
 175          */
 176         int i, ret;
 177         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 178                 switch (i) {
 179                 case 0:
 180                         imx_iomux_v3_setup_multiple_pads(
 181                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 182                         gpio_request(USDHC2_CD_GPIO, "MMC0_CD");
 183                         gpio_direction_input(USDHC2_CD_GPIO);
 184                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 185                         break;
 186                 case 1:
 187                         imx_iomux_v3_setup_multiple_pads(
 188                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 189                         gpio_request(USDHC3_CD_GPIO, "MMC1_CD");
 190                         gpio_direction_input(USDHC3_CD_GPIO);
 191                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 192                         break;
 193                 case 2:
 194                         imx_iomux_v3_setup_multiple_pads(
 195                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 196                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 197                         break;
 198                 default:
 199                         printf("Warning: you configured more USDHC controllers"
 200                                "(%d) then supported by the board (%d)\n",
 201                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 202                         return -EINVAL;
 203                 }
 204                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 205                 if (ret)
 206                         return ret;
 207         }
 208         return 0;
 209 }
 210
 211 /* set environment device to boot device when booting from SD */
 212 int board_mmc_get_env_dev(int devno)
 213 {
 214         return devno - 1;
 215 }
 216
 217 int board_mmc_get_env_part(int devno)
 218 {
 219         return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
 220 }
 221 #endif /* CONFIG_FSL_ESDHC */
 222
 223 #ifdef CONFIG_VIDEO_IPUV3
 224 static void do_enable_hdmi(struct display_info_t const *dev)
 225 {
 226         imx_enable_hdmi_phy();
 227 }
 228
 229 struct display_info_t const displays[] = {{
 230         .bus    = -1,
 231         .addr   = 0,
 232         .pixfmt = IPU_PIX_FMT_RGB24,
 233         .detect = detect_hdmi,
 234         .enable = do_enable_hdmi,
 235         .mode   = {
 236                 .name           = "HDMI",
 237                 /* 1024x768@60Hz (VESA)*/
 238                 .refresh        = 60,
 239                 .xres           = 1024,
 240                 .yres           = 768,
 241                 .pixclock       = 15384,
 242                 .left_margin    = 160,
 243                 .right_margin   = 24,
 244                 .upper_margin   = 29,
 245                 .lower_margin   = 3,
 246                 .hsync_len      = 136,
 247                 .vsync_len      = 6,
 248                 .sync           = FB_SYNC_EXT,
 249                 .vmode          = FB_VMODE_NONINTERLACED
 250 } } };
 251 size_t display_count = ARRAY_SIZE(displays);
 252
 253 static void setup_display(void)
 254 {
 255         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 256         int reg;
 257         s32 timeout = 100000;
 258
 259         enable_ipu_clock();
 260         imx_setup_hdmi();
 261
 262         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 263         reg = readl(&ccm->analog_pll_video);
 264         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 265         writel(reg, &ccm->analog_pll_video);
 266
 267         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 268         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 269         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 270         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 271         writel(reg, &ccm->analog_pll_video);
 272
 273         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 274         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 275
 276         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 277         writel(reg, &ccm->analog_pll_video);
 278
 279         while (timeout--)
 280                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 281                         break;
 282         if (timeout < 0)
 283                 printf("Warning: video pll lock timeout!\n");
 284
 285         reg = readl(&ccm->analog_pll_video);
 286         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 287         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 288         writel(reg, &ccm->analog_pll_video);
 289
 290         /* gate ipu1_di0_clk */
 291         reg = readl(&ccm->CCGR3);
 292         reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
 293         writel(reg, &ccm->CCGR3);
 294
 295         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 296         reg = readl(&ccm->chsccdr);
 297         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 298                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 299                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 300         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 301                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 302                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 303         writel(reg, &ccm->chsccdr);
 304
 305         /* enable ipu1_di0_clk */
 306         reg = readl(&ccm->CCGR3);
 307         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 308         writel(reg, &ccm->CCGR3);
 309 }
 310 #endif /* CONFIG_VIDEO_IPUV3 */
 311
 312 static int ar8035_phy_fixup(struct phy_device *phydev)
 313 {
 314         unsigned short val;
 315
 316         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 317         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 318         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 319         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 320
 321         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 322         val &= 0xffe3;
 323         val |= 0x18;
 324         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 325
 326         /* introduce tx clock delay */
 327         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 328         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 329         val |= 0x0100;
 330         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 331
 332         return 0;
 333 }
 334
 335 int board_phy_config(struct phy_device *phydev)
 336 {
 337         ar8035_phy_fixup(phydev);
 338
 339         if (phydev->drv->config)
 340                 phydev->drv->config(phydev);
 341
 342         return 0;
 343 }
 344
 345 int board_eth_init(bd_t *bis)
 346 {
 347         setup_iomux_enet();
 348         setup_pcie();
 349         return cpu_eth_init(bis);
 350 }
 351
 352 int board_early_init_f(void)
 353 {
 354         setup_iomux_uart();
 355         return 0;
 356 }
 357
 358 #ifdef CONFIG_CMD_BMODE
 359 static const struct boot_mode board_boot_modes[] = {
 360         /* 4 bit bus width */
 361         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 362         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 363         /* 8 bit bus width */
 364         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 365         {NULL,   0},
 366 };
 367 #endif
 368
 369 int board_init(void)
 370 {
 371         /* address of boot parameters */
 372         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 373
 374 #ifdef CONFIG_VIDEO_IPUV3
 375         setup_display();
 376 #endif
 377 #ifdef CONFIG_DWC_AHSATA
 378         setup_sata();
 379 #endif
 380 #ifdef CONFIG_CMD_BMODE
 381         add_board_boot_modes(board_boot_modes);
 382 #endif
 383         return 0;
 384 }