board/tbs/tbs2910/tbs2910.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
   4  */
   5
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/imx-regs.h>
   8 #include <asm/arch/iomux.h>
   9 #include <asm/arch/mx6-pins.h>
  10 #include <linux/errno.h>
  11 #include <asm/gpio.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/mach-imx/boot_mode.h>
  14 #include <asm/mach-imx/video.h>
  15 #include <mmc.h>
  16 #include <fsl_esdhc_imx.h>
  17 #include <miiphy.h>
  18 #include <netdev.h>
  19 #include <asm/arch/mxc_hdmi.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/sys_proto.h>
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define WEAK_PULLUP     (PAD_CTL_PUS_47K_UP |                   \
  26         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  27         PAD_CTL_SRE_SLOW)
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  30         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  31         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  34         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  35
  36 static iomux_v3_cfg_t const uart1_pads[] = {
  37         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  38         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  39 };
  40
  41 static iomux_v3_cfg_t const uart2_pads[] = {
  42         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  43         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  44 };
  45
  46 static iomux_v3_cfg_t const enet_pads[] = {
  47         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  48         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  49         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  50         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  51         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  52         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  53         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  56         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         /* AR8035 PHY Reset */
  63         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  64 };
  65
  66 static iomux_v3_cfg_t const pcie_pads[] = {
  67         /* W_DISABLE# */
  68         MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
  69         /* PERST# */
  70         MX6_PAD_GPIO_17__GPIO7_IO12  | MUX_PAD_CTRL(NO_PAD_CTRL),
  71 };
  72
  73 int dram_init(void)
  74 {
  75         gd->ram_size = 2048ul * 1024 * 1024;
  76         return 0;
  77 }
  78
  79 static void setup_iomux_enet(void)
  80 {
  81         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  82
  83         /* Reset AR8035 PHY */
  84         gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
  85         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  86         udelay(500);
  87         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  88 }
  89
  90 static void setup_pcie(void)
  91 {
  92         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  93 }
  94
  95 static void setup_iomux_uart(void)
  96 {
  97         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  98         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  99 }
 100
 101 #ifdef CONFIG_FSL_ESDHC_IMX
 102 /* set environment device to boot device when booting from SD */
 103 int board_mmc_get_env_dev(int devno)
 104 {
 105         return devno - 1;
 106 }
 107
 108 int board_mmc_get_env_part(int devno)
 109 {
 110         return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
 111 }
 112 #endif /* CONFIG_FSL_ESDHC_IMX */
 113
 114 #ifdef CONFIG_VIDEO_IPUV3
 115 static void do_enable_hdmi(struct display_info_t const *dev)
 116 {
 117         imx_enable_hdmi_phy();
 118 }
 119
 120 struct display_info_t const displays[] = {{
 121         .bus    = -1,
 122         .addr   = 0,
 123         .pixfmt = IPU_PIX_FMT_RGB24,
 124         .detect = detect_hdmi,
 125         .enable = do_enable_hdmi,
 126         .mode   = {
 127                 .name           = "HDMI",
 128                 /* 1024x768@60Hz (VESA)*/
 129                 .refresh        = 60,
 130                 .xres           = 1024,
 131                 .yres           = 768,
 132                 .pixclock       = 15384,
 133                 .left_margin    = 160,
 134                 .right_margin   = 24,
 135                 .upper_margin   = 29,
 136                 .lower_margin   = 3,
 137                 .hsync_len      = 136,
 138                 .vsync_len      = 6,
 139                 .sync           = FB_SYNC_EXT,
 140                 .vmode          = FB_VMODE_NONINTERLACED
 141 } } };
 142 size_t display_count = ARRAY_SIZE(displays);
 143
 144 static void setup_display(void)
 145 {
 146         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 147         int reg;
 148         s32 timeout = 100000;
 149
 150         enable_ipu_clock();
 151         imx_setup_hdmi();
 152
 153         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 154         reg = readl(&ccm->analog_pll_video);
 155         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 156         writel(reg, &ccm->analog_pll_video);
 157
 158         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 159         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 160         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 161         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 162         writel(reg, &ccm->analog_pll_video);
 163
 164         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 165         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 166
 167         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 168         writel(reg, &ccm->analog_pll_video);
 169
 170         while (timeout--)
 171                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 172                         break;
 173         if (timeout < 0)
 174                 printf("Warning: video pll lock timeout!\n");
 175
 176         reg = readl(&ccm->analog_pll_video);
 177         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 178         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 179         writel(reg, &ccm->analog_pll_video);
 180
 181         /* gate ipu1_di0_clk */
 182         reg = readl(&ccm->CCGR3);
 183         reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
 184         writel(reg, &ccm->CCGR3);
 185
 186         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 187         reg = readl(&ccm->chsccdr);
 188         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 189                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 190                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 191         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 192                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 193                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 194         writel(reg, &ccm->chsccdr);
 195
 196         /* enable ipu1_di0_clk */
 197         reg = readl(&ccm->CCGR3);
 198         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 199         writel(reg, &ccm->CCGR3);
 200 }
 201 #endif /* CONFIG_VIDEO_IPUV3 */
 202
 203 static int ar8035_phy_fixup(struct phy_device *phydev)
 204 {
 205         unsigned short val;
 206
 207         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 208         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 209         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 210         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 211
 212         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 213         val &= 0xffe3;
 214         val |= 0x18;
 215         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 216
 217         /* introduce tx clock delay */
 218         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 219         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 220         val |= 0x0100;
 221         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 222
 223         return 0;
 224 }
 225
 226 int board_phy_config(struct phy_device *phydev)
 227 {
 228         ar8035_phy_fixup(phydev);
 229
 230         if (phydev->drv->config)
 231                 phydev->drv->config(phydev);
 232
 233         return 0;
 234 }
 235
 236 int board_eth_init(bd_t *bis)
 237 {
 238         setup_iomux_enet();
 239         setup_pcie();
 240         return cpu_eth_init(bis);
 241 }
 242
 243 int board_early_init_f(void)
 244 {
 245         setup_iomux_uart();
 246         return 0;
 247 }
 248
 249 #ifdef CONFIG_CMD_BMODE
 250 static const struct boot_mode board_boot_modes[] = {
 251         /* 4 bit bus width */
 252         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 253         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 254         /* 8 bit bus width */
 255         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 256         {NULL,   0},
 257 };
 258 #endif
 259
 260 int board_init(void)
 261 {
 262         /* address of boot parameters */
 263         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 264
 265 #ifdef CONFIG_VIDEO_IPUV3
 266         setup_display();
 267 #endif
 268 #ifdef CONFIG_CMD_BMODE
 269         add_board_boot_modes(board_boot_modes);
 270 #endif
 271         return 0;
 272 }