board/tcl/sl50/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TCL SL50 board
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <errno.h>
  13 #include <init.h>
  14 #include <serial.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mem.h>
  25 #include <asm/io.h>
  26 #include <asm/emif.h>
  27 #include <asm/gpio.h>
  28 #include <i2c.h>
  29 #include <miiphy.h>
  30 #include <cpsw.h>
  31 #include <power/tps65217.h>
  32 #include <power/tps65910.h>
  33 #include <env_internal.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  40
  41 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  42
  43 static const struct ddr_data ddr3_sl50_data = {
  44         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  45         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  46         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  47         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  48 };
  49
  50 static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
  51         .cmd0csratio = MT41K256M16HA125E_RATIO,
  52         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  53
  54         .cmd1csratio = MT41K256M16HA125E_RATIO,
  55         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  56
  57         .cmd2csratio = MT41K256M16HA125E_RATIO,
  58         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  59 };
  60
  61 static struct emif_regs ddr3_sl50_emif_reg_data = {
  62         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  63         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  64         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  65         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  66         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  67         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  68         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  69 };
  70
  71 #ifdef CONFIG_SPL_OS_BOOT
  72 int spl_start_uboot(void)
  73 {
  74         /* break into full u-boot on 'c' */
  75         if (serial_tstc() && serial_getc() == 'c')
  76                 return 1;
  77
  78 #ifdef CONFIG_SPL_ENV_SUPPORT
  79         env_init();
  80         env_load();
  81         if (env_get_yesno("boot_os") != 1)
  82                 return 1;
  83 #endif
  84
  85         return 0;
  86 }
  87 #endif
  88
  89 #define OSC     (V_OSCK/1000000)
  90 const struct dpll_params dpll_ddr_sl50 = {
  91                 400, OSC-1, 1, -1, -1, -1, -1};
  92
  93 void am33xx_spl_board_init(void)
  94 {
  95         int mpu_vdd;
  96
  97         /* Get the frequency */
  98         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  99
 100         /* BeagleBone PMIC Code */
 101         int usb_cur_lim;
 102
 103         if (i2c_probe(TPS65217_CHIP_PM))
 104                 return;
 105
 106         /*
 107          * Increase USB current limit to 1300mA or 1800mA and set
 108          * the MPU voltage controller as needed.
 109          */
 110         if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 111                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 112                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 113         } else {
 114                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 115                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 116         }
 117
 118         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 119                                TPS65217_POWER_PATH,
 120                                usb_cur_lim,
 121                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 122                 puts("tps65217_reg_write failure\n");
 123
 124         /* Set DCDC3 (CORE) voltage to 1.125V */
 125         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 126                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 127                 puts("tps65217_voltage_update failure\n");
 128                 return;
 129         }
 130
 131         /* Set CORE Frequencies to OPP100 */
 132         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 133
 134         /* Set DCDC2 (MPU) voltage */
 135         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 136                 puts("tps65217_voltage_update failure\n");
 137                 return;
 138         }
 139
 140         /*
 141          * Set LDO3 to 1.8V and LDO4 to 3.3V
 142          */
 143         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 144                                TPS65217_DEFLS1,
 145                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 146                                TPS65217_LDO_MASK))
 147                 puts("tps65217_reg_write failure\n");
 148
 149         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 150                                TPS65217_DEFLS2,
 151                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 152                                TPS65217_LDO_MASK))
 153                 puts("tps65217_reg_write failure\n");
 154
 155         /* Set MPU Frequency to what we detected now that voltages are set */
 156         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 157 }
 158
 159 const struct dpll_params *get_dpll_ddr_params(void)
 160 {
 161         enable_i2c0_pin_mux();
 162         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 163
 164         return &dpll_ddr_sl50;
 165 }
 166
 167 void set_uart_mux_conf(void)
 168 {
 169 #if CONFIG_CONS_INDEX == 1
 170         enable_uart0_pin_mux();
 171 #elif CONFIG_CONS_INDEX == 2
 172         enable_uart1_pin_mux();
 173 #elif CONFIG_CONS_INDEX == 3
 174         enable_uart2_pin_mux();
 175 #elif CONFIG_CONS_INDEX == 4
 176         enable_uart3_pin_mux();
 177 #elif CONFIG_CONS_INDEX == 5
 178         enable_uart4_pin_mux();
 179 #elif CONFIG_CONS_INDEX == 6
 180         enable_uart5_pin_mux();
 181 #endif
 182 }
 183
 184 void set_mux_conf_regs(void)
 185 {
 186         enable_board_pin_mux();
 187 }
 188
 189 const struct ctrl_ioregs ioregs_evmsk = {
 190         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 191         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 192         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 193         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 194         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 195 };
 196
 197 const struct ctrl_ioregs ioregs_bonelt = {
 198         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 199         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 200         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 201         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 202         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 203 };
 204
 205 const struct ctrl_ioregs ioregs_evm15 = {
 206         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 207         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 208         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 209         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 210         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 211 };
 212
 213 const struct ctrl_ioregs ioregs = {
 214         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 215         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 216         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 217         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 218         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 219 };
 220
 221 void sdram_init(void)
 222 {
 223         config_ddr(400, &ioregs_bonelt,
 224                    &ddr3_sl50_data,
 225                    &ddr3_sl50_cmd_ctrl_data,
 226                    &ddr3_sl50_emif_reg_data, 0);
 227 }
 228 #endif
 229
 230 /*
 231  * Basic board specific setup.  Pinmux has been handled already.
 232  */
 233 int board_init(void)
 234 {
 235 #if defined(CONFIG_HW_WATCHDOG)
 236         hw_watchdog_init();
 237 #endif
 238
 239         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 240         return 0;
 241 }
 242
 243 #ifdef CONFIG_BOARD_LATE_INIT
 244 int board_late_init(void)
 245 {
 246         return 0;
 247 }
 248 #endif
 249
 250 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 251         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 252 static void cpsw_control(int enabled)
 253 {
 254         /* VTP can be added here */
 255
 256         return;
 257 }
 258
 259 static struct cpsw_slave_data cpsw_slaves[] = {
 260         {
 261                 .slave_reg_ofs  = 0x208,
 262                 .sliver_reg_ofs = 0xd80,
 263                 .phy_addr       = 0,
 264         },
 265         {
 266                 .slave_reg_ofs  = 0x308,
 267                 .sliver_reg_ofs = 0xdc0,
 268                 .phy_addr       = 1,
 269         },
 270 };
 271
 272 static struct cpsw_platform_data cpsw_data = {
 273         .mdio_base              = CPSW_MDIO_BASE,
 274         .cpsw_base              = CPSW_BASE,
 275         .mdio_div               = 0xff,
 276         .channels               = 8,
 277         .cpdma_reg_ofs          = 0x800,
 278         .slaves                 = 1,
 279         .slave_data             = cpsw_slaves,
 280         .ale_reg_ofs            = 0xd00,
 281         .ale_entries            = 1024,
 282         .host_port_reg_ofs      = 0x108,
 283         .hw_stats_reg_ofs       = 0x900,
 284         .bd_ram_ofs             = 0x2000,
 285         .mac_control            = (1 << 5),
 286         .control                = cpsw_control,
 287         .host_port_num          = 0,
 288         .version                = CPSW_CTRL_VERSION_2,
 289 };
 290 #endif
 291
 292 /*
 293  * This function will:
 294  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 295  * in the environment
 296  * Perform fixups to the PHY present on certain boards.  We only need this
 297  * function in:
 298  * - SPL with either CPSW or USB ethernet support
 299  * - Full U-Boot, with either CPSW or USB ethernet
 300  * Build in only these cases to avoid warnings about unused variables
 301  * when we build an SPL that has neither option but full U-Boot will.
 302  */
 303 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
 304                 && defined(CONFIG_SPL_BUILD)) || \
 305         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 306           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 307          !defined(CONFIG_SPL_BUILD))
 308 int board_eth_init(bd_t *bis)
 309 {
 310         int rv, n = 0;
 311         uint8_t mac_addr[6];
 312         uint32_t mac_hi, mac_lo;
 313
 314         /* try reading mac address from efuse */
 315         mac_lo = readl(&cdev->macid0l);
 316         mac_hi = readl(&cdev->macid0h);
 317         mac_addr[0] = mac_hi & 0xFF;
 318         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 319         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 320         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 321         mac_addr[4] = mac_lo & 0xFF;
 322         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 323
 324 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 325         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 326         if (!env_get("ethaddr")) {
 327                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 328
 329                 if (is_valid_ethaddr(mac_addr))
 330                         eth_env_set_enetaddr("ethaddr", mac_addr);
 331         }
 332
 333 #ifdef CONFIG_DRIVER_TI_CPSW
 334
 335         mac_lo = readl(&cdev->macid1l);
 336         mac_hi = readl(&cdev->macid1h);
 337         mac_addr[0] = mac_hi & 0xFF;
 338         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 339         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 340         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 341         mac_addr[4] = mac_lo & 0xFF;
 342         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 343
 344         if (!env_get("eth1addr")) {
 345                 if (is_valid_ethaddr(mac_addr))
 346                         eth_env_set_enetaddr("eth1addr", mac_addr);
 347         }
 348
 349
 350         writel(MII_MODE_ENABLE, &cdev->miisel);
 351         cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 352                                 PHY_INTERFACE_MODE_MII;
 353
 354         rv = cpsw_register(&cpsw_data);
 355         if (rv < 0)
 356                 printf("Error %d registering CPSW switch\n", rv);
 357         else
 358                 n += rv;
 359 #endif
 360
 361         /*
 362          *
 363          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 364          * operating points.  So we must set the TX clock delay feature
 365          * in the AR8051 PHY.  Since we only support a single ethernet
 366          * device in U-Boot, we only do this for the first instance.
 367          */
 368 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 369 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 370 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 371 #define AR8051_RGMII_TX_CLK_DLY         0x100
 372
 373 #endif
 374 #if defined(CONFIG_USB_ETHER) && \
 375         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
 376         if (is_valid_ether_addr(mac_addr))
 377                 eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
 378
 379         rv = usb_eth_initialize(bis);
 380         if (rv < 0)
 381                 printf("Error %d registering USB_ETHER\n", rv);
 382         else
 383                 n += rv;
 384 #endif
 385         return n;
 386 }
 387 #endif