1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM335X based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/clk_synthesizer.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/mem.h>
28 #include <asm/omap_common.h>
29 #include <asm/omap_sec_common.h>
30 #include <asm/omap_mmc.h>
34 #include <power/tps65217.h>
35 #include <power/tps65910.h>
36 #include <environment.h>
38 #include <environment.h>
39 #include "../common/board_detect.h"
42 DECLARE_GLOBAL_DATA_PTR
;
44 /* GPIO that controls power to DDR on EVM-SK */
45 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
46 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
47 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
48 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
49 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
50 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
51 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
52 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
53 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
55 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
57 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
58 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
60 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
61 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
63 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
64 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
67 * Read header information from EEPROM into global structure.
69 #ifdef CONFIG_TI_I2C_BOARD_DETECT
70 void do_board_detect(void)
72 enable_i2c0_pin_mux();
73 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
75 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
76 CONFIG_EEPROM_CHIP_ADDRESS
))
77 printf("ti_i2c_eeprom_init failed\n");
81 #ifndef CONFIG_DM_SERIAL
82 struct serial_device
*default_serial_console(void)
85 return &eserial4_device
;
87 return &eserial1_device
;
91 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
92 static const struct ddr_data ddr2_data
= {
93 .datardsratio0
= MT47H128M16RT25E_RD_DQS
,
94 .datafwsratio0
= MT47H128M16RT25E_PHY_FIFO_WE
,
95 .datawrsratio0
= MT47H128M16RT25E_PHY_WR_DATA
,
98 static const struct cmd_control ddr2_cmd_ctrl_data
= {
99 .cmd0csratio
= MT47H128M16RT25E_RATIO
,
101 .cmd1csratio
= MT47H128M16RT25E_RATIO
,
103 .cmd2csratio
= MT47H128M16RT25E_RATIO
,
106 static const struct emif_regs ddr2_emif_reg_data
= {
107 .sdram_config
= MT47H128M16RT25E_EMIF_SDCFG
,
108 .ref_ctrl
= MT47H128M16RT25E_EMIF_SDREF
,
109 .sdram_tim1
= MT47H128M16RT25E_EMIF_TIM1
,
110 .sdram_tim2
= MT47H128M16RT25E_EMIF_TIM2
,
111 .sdram_tim3
= MT47H128M16RT25E_EMIF_TIM3
,
112 .emif_ddr_phy_ctlr_1
= MT47H128M16RT25E_EMIF_READ_LATENCY
,
115 static const struct emif_regs ddr2_evm_emif_reg_data
= {
116 .sdram_config
= MT47H128M16RT25E_EMIF_SDCFG
,
117 .ref_ctrl
= MT47H128M16RT25E_EMIF_SDREF
,
118 .sdram_tim1
= MT47H128M16RT25E_EMIF_TIM1
,
119 .sdram_tim2
= MT47H128M16RT25E_EMIF_TIM2
,
120 .sdram_tim3
= MT47H128M16RT25E_EMIF_TIM3
,
121 .ocp_config
= EMIF_OCP_CONFIG_AM335X_EVM
,
122 .emif_ddr_phy_ctlr_1
= MT47H128M16RT25E_EMIF_READ_LATENCY
,
125 static const struct ddr_data ddr3_data
= {
126 .datardsratio0
= MT41J128MJT125_RD_DQS
,
127 .datawdsratio0
= MT41J128MJT125_WR_DQS
,
128 .datafwsratio0
= MT41J128MJT125_PHY_FIFO_WE
,
129 .datawrsratio0
= MT41J128MJT125_PHY_WR_DATA
,
132 static const struct ddr_data ddr3_beagleblack_data
= {
133 .datardsratio0
= MT41K256M16HA125E_RD_DQS
,
134 .datawdsratio0
= MT41K256M16HA125E_WR_DQS
,
135 .datafwsratio0
= MT41K256M16HA125E_PHY_FIFO_WE
,
136 .datawrsratio0
= MT41K256M16HA125E_PHY_WR_DATA
,
139 static const struct ddr_data ddr3_evm_data
= {
140 .datardsratio0
= MT41J512M8RH125_RD_DQS
,
141 .datawdsratio0
= MT41J512M8RH125_WR_DQS
,
142 .datafwsratio0
= MT41J512M8RH125_PHY_FIFO_WE
,
143 .datawrsratio0
= MT41J512M8RH125_PHY_WR_DATA
,
146 static const struct ddr_data ddr3_icev2_data
= {
147 .datardsratio0
= MT41J128MJT125_RD_DQS_400MHz
,
148 .datawdsratio0
= MT41J128MJT125_WR_DQS_400MHz
,
149 .datafwsratio0
= MT41J128MJT125_PHY_FIFO_WE_400MHz
,
150 .datawrsratio0
= MT41J128MJT125_PHY_WR_DATA_400MHz
,
153 static const struct cmd_control ddr3_cmd_ctrl_data
= {
154 .cmd0csratio
= MT41J128MJT125_RATIO
,
155 .cmd0iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
157 .cmd1csratio
= MT41J128MJT125_RATIO
,
158 .cmd1iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
160 .cmd2csratio
= MT41J128MJT125_RATIO
,
161 .cmd2iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
164 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data
= {
165 .cmd0csratio
= MT41K256M16HA125E_RATIO
,
166 .cmd0iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
168 .cmd1csratio
= MT41K256M16HA125E_RATIO
,
169 .cmd1iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
171 .cmd2csratio
= MT41K256M16HA125E_RATIO
,
172 .cmd2iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
175 static const struct cmd_control ddr3_evm_cmd_ctrl_data
= {
176 .cmd0csratio
= MT41J512M8RH125_RATIO
,
177 .cmd0iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
179 .cmd1csratio
= MT41J512M8RH125_RATIO
,
180 .cmd1iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
182 .cmd2csratio
= MT41J512M8RH125_RATIO
,
183 .cmd2iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
186 static const struct cmd_control ddr3_icev2_cmd_ctrl_data
= {
187 .cmd0csratio
= MT41J128MJT125_RATIO_400MHz
,
188 .cmd0iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
190 .cmd1csratio
= MT41J128MJT125_RATIO_400MHz
,
191 .cmd1iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
193 .cmd2csratio
= MT41J128MJT125_RATIO_400MHz
,
194 .cmd2iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
197 static struct emif_regs ddr3_emif_reg_data
= {
198 .sdram_config
= MT41J128MJT125_EMIF_SDCFG
,
199 .ref_ctrl
= MT41J128MJT125_EMIF_SDREF
,
200 .sdram_tim1
= MT41J128MJT125_EMIF_TIM1
,
201 .sdram_tim2
= MT41J128MJT125_EMIF_TIM2
,
202 .sdram_tim3
= MT41J128MJT125_EMIF_TIM3
,
203 .zq_config
= MT41J128MJT125_ZQ_CFG
,
204 .emif_ddr_phy_ctlr_1
= MT41J128MJT125_EMIF_READ_LATENCY
|
208 static struct emif_regs ddr3_beagleblack_emif_reg_data
= {
209 .sdram_config
= MT41K256M16HA125E_EMIF_SDCFG
,
210 .ref_ctrl
= MT41K256M16HA125E_EMIF_SDREF
,
211 .sdram_tim1
= MT41K256M16HA125E_EMIF_TIM1
,
212 .sdram_tim2
= MT41K256M16HA125E_EMIF_TIM2
,
213 .sdram_tim3
= MT41K256M16HA125E_EMIF_TIM3
,
214 .ocp_config
= EMIF_OCP_CONFIG_BEAGLEBONE_BLACK
,
215 .zq_config
= MT41K256M16HA125E_ZQ_CFG
,
216 .emif_ddr_phy_ctlr_1
= MT41K256M16HA125E_EMIF_READ_LATENCY
,
219 static struct emif_regs ddr3_evm_emif_reg_data
= {
220 .sdram_config
= MT41J512M8RH125_EMIF_SDCFG
,
221 .ref_ctrl
= MT41J512M8RH125_EMIF_SDREF
,
222 .sdram_tim1
= MT41J512M8RH125_EMIF_TIM1
,
223 .sdram_tim2
= MT41J512M8RH125_EMIF_TIM2
,
224 .sdram_tim3
= MT41J512M8RH125_EMIF_TIM3
,
225 .ocp_config
= EMIF_OCP_CONFIG_AM335X_EVM
,
226 .zq_config
= MT41J512M8RH125_ZQ_CFG
,
227 .emif_ddr_phy_ctlr_1
= MT41J512M8RH125_EMIF_READ_LATENCY
|
231 static struct emif_regs ddr3_icev2_emif_reg_data
= {
232 .sdram_config
= MT41J128MJT125_EMIF_SDCFG_400MHz
,
233 .ref_ctrl
= MT41J128MJT125_EMIF_SDREF_400MHz
,
234 .sdram_tim1
= MT41J128MJT125_EMIF_TIM1_400MHz
,
235 .sdram_tim2
= MT41J128MJT125_EMIF_TIM2_400MHz
,
236 .sdram_tim3
= MT41J128MJT125_EMIF_TIM3_400MHz
,
237 .zq_config
= MT41J128MJT125_ZQ_CFG_400MHz
,
238 .emif_ddr_phy_ctlr_1
= MT41J128MJT125_EMIF_READ_LATENCY_400MHz
|
242 #ifdef CONFIG_SPL_OS_BOOT
243 int spl_start_uboot(void)
245 #ifdef CONFIG_SPL_SERIAL_SUPPORT
246 /* break into full u-boot on 'c' */
247 if (serial_tstc() && serial_getc() == 'c')
251 #ifdef CONFIG_SPL_ENV_SUPPORT
254 if (env_get_yesno("boot_os") != 1)
262 const struct dpll_params
*get_dpll_ddr_params(void)
264 int ind
= get_sys_clk_index();
266 if (board_is_evm_sk())
267 return &dpll_ddr3_303MHz
[ind
];
268 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
269 return &dpll_ddr3_400MHz
[ind
];
270 else if (board_is_evm_15_or_later())
271 return &dpll_ddr3_303MHz
[ind
];
273 return &dpll_ddr2_266MHz
[ind
];
276 static u8
bone_not_connected_to_ac_power(void)
278 if (board_is_bone()) {
279 uchar pmic_status_reg
;
280 if (tps65217_reg_read(TPS65217_STATUS
,
283 if (!(pmic_status_reg
& TPS65217_PWR_SRC_AC_BITMASK
)) {
284 puts("No AC power, switching to default OPP\n");
291 const struct dpll_params
*get_dpll_mpu_params(void)
293 int ind
= get_sys_clk_index();
294 int freq
= am335x_get_efuse_mpu_max_freq(cdev
);
296 if (bone_not_connected_to_ac_power())
299 if (board_is_pb() || board_is_bone_lt())
300 freq
= MPUPLL_M_1000
;
304 return &dpll_mpu_opp
[ind
][5];
306 return &dpll_mpu_opp
[ind
][4];
308 return &dpll_mpu_opp
[ind
][3];
310 return &dpll_mpu_opp
[ind
][2];
312 return &dpll_mpu_opp100
;
314 return &dpll_mpu_opp
[ind
][0];
317 return &dpll_mpu_opp
[ind
][0];
320 static void scale_vcores_bone(int freq
)
322 int usb_cur_lim
, mpu_vdd
;
325 * Only perform PMIC configurations if board rev > A1
326 * on Beaglebone White
328 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
331 if (i2c_probe(TPS65217_CHIP_PM
))
335 * On Beaglebone White we need to ensure we have AC power
336 * before increasing the frequency.
338 if (bone_not_connected_to_ac_power())
342 * Override what we have detected since we know if we have
343 * a Beaglebone Black it supports 1GHz.
345 if (board_is_pb() || board_is_bone_lt())
346 freq
= MPUPLL_M_1000
;
350 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1325MV
;
351 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1800MA
;
354 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1275MV
;
355 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
358 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1200MV
;
359 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
365 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1100MV
;
366 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
370 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE
,
373 TPS65217_USB_INPUT_CUR_LIMIT_MASK
))
374 puts("tps65217_reg_write failure\n");
376 /* Set DCDC3 (CORE) voltage to 1.10V */
377 if (tps65217_voltage_update(TPS65217_DEFDCDC3
,
378 TPS65217_DCDC_VOLT_SEL_1100MV
)) {
379 puts("tps65217_voltage_update failure\n");
383 /* Set DCDC2 (MPU) voltage */
384 if (tps65217_voltage_update(TPS65217_DEFDCDC2
, mpu_vdd
)) {
385 puts("tps65217_voltage_update failure\n");
390 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
391 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
393 if (board_is_bone()) {
394 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
396 TPS65217_LDO_VOLTAGE_OUT_3_3
,
398 puts("tps65217_reg_write failure\n");
400 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
402 TPS65217_LDO_VOLTAGE_OUT_1_8
,
404 puts("tps65217_reg_write failure\n");
407 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
409 TPS65217_LDO_VOLTAGE_OUT_3_3
,
411 puts("tps65217_reg_write failure\n");
414 void scale_vcores_generic(int freq
)
416 int sil_rev
, mpu_vdd
;
419 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
420 * MPU frequencies we support we use a CORE voltage of
421 * 1.10V. For MPU voltage we need to switch based on
422 * the frequency we are running at.
424 if (i2c_probe(TPS65910_CTRL_I2C_ADDR
))
428 * Depending on MPU clock and PG we will need a different
429 * VDD to drive at that speed.
431 sil_rev
= readl(&cdev
->deviceid
) >> 28;
432 mpu_vdd
= am335x_get_tps65910_mpu_vdd(sil_rev
, freq
);
434 /* Tell the TPS65910 to use i2c */
435 tps65910_set_i2c_control();
437 /* First update MPU voltage. */
438 if (tps65910_voltage_update(MPU
, mpu_vdd
))
441 /* Second, update the CORE voltage. */
442 if (tps65910_voltage_update(CORE
, TPS65910_OP_REG_SEL_1_1_0
))
447 void gpi2c_init(void)
449 /* When needed to be invoked prior to BSS initialization */
450 static bool first_time
= true;
453 enable_i2c0_pin_mux();
454 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
,
455 CONFIG_SYS_OMAP24_I2C_SLAVE
);
460 void scale_vcores(void)
465 freq
= am335x_get_efuse_mpu_max_freq(cdev
);
467 if (board_is_beaglebonex())
468 scale_vcores_bone(freq
);
470 scale_vcores_generic(freq
);
473 void set_uart_mux_conf(void)
475 #if CONFIG_CONS_INDEX == 1
476 enable_uart0_pin_mux();
477 #elif CONFIG_CONS_INDEX == 2
478 enable_uart1_pin_mux();
479 #elif CONFIG_CONS_INDEX == 3
480 enable_uart2_pin_mux();
481 #elif CONFIG_CONS_INDEX == 4
482 enable_uart3_pin_mux();
483 #elif CONFIG_CONS_INDEX == 5
484 enable_uart4_pin_mux();
485 #elif CONFIG_CONS_INDEX == 6
486 enable_uart5_pin_mux();
490 void set_mux_conf_regs(void)
492 enable_board_pin_mux();
495 const struct ctrl_ioregs ioregs_evmsk
= {
496 .cm0ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
497 .cm1ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
498 .cm2ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
499 .dt0ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
500 .dt1ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
503 const struct ctrl_ioregs ioregs_bonelt
= {
504 .cm0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
505 .cm1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
506 .cm2ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
507 .dt0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
508 .dt1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
511 const struct ctrl_ioregs ioregs_evm15
= {
512 .cm0ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
513 .cm1ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
514 .cm2ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
515 .dt0ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
516 .dt1ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
519 const struct ctrl_ioregs ioregs
= {
520 .cm0ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
521 .cm1ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
522 .cm2ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
523 .dt0ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
524 .dt1ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
527 void sdram_init(void)
529 if (board_is_evm_sk()) {
531 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
532 * This is safe enough to do on older revs.
534 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
535 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
538 if (board_is_icev2()) {
539 gpio_request(ICE_GPIO_DDR_VTT_EN
, "ddr_vtt_en");
540 gpio_direction_output(ICE_GPIO_DDR_VTT_EN
, 1);
543 if (board_is_evm_sk())
544 config_ddr(303, &ioregs_evmsk
, &ddr3_data
,
545 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
546 else if (board_is_pb() || board_is_bone_lt())
547 config_ddr(400, &ioregs_bonelt
,
548 &ddr3_beagleblack_data
,
549 &ddr3_beagleblack_cmd_ctrl_data
,
550 &ddr3_beagleblack_emif_reg_data
, 0);
551 else if (board_is_evm_15_or_later())
552 config_ddr(303, &ioregs_evm15
, &ddr3_evm_data
,
553 &ddr3_evm_cmd_ctrl_data
, &ddr3_evm_emif_reg_data
, 0);
554 else if (board_is_icev2())
555 config_ddr(400, &ioregs_evmsk
, &ddr3_icev2_data
,
556 &ddr3_icev2_cmd_ctrl_data
, &ddr3_icev2_emif_reg_data
,
558 else if (board_is_gp_evm())
559 config_ddr(266, &ioregs
, &ddr2_data
,
560 &ddr2_cmd_ctrl_data
, &ddr2_evm_emif_reg_data
, 0);
562 config_ddr(266, &ioregs
, &ddr2_data
,
563 &ddr2_cmd_ctrl_data
, &ddr2_emif_reg_data
, 0);
567 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
568 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
569 static void request_and_set_gpio(int gpio
, char *name
, int val
)
573 ret
= gpio_request(gpio
, name
);
575 printf("%s: Unable to request %s\n", __func__
, name
);
579 ret
= gpio_direction_output(gpio
, 0);
581 printf("%s: Unable to set %s as output\n", __func__
, name
);
585 gpio_set_value(gpio
, val
);
593 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
594 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
597 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
598 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
599 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
600 * give 50MHz output for Eth0 and 1.
602 static struct clk_synth cdce913_data
= {
611 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
612 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
614 #define MAX_CPSW_SLAVES 2
616 /* At the moment, we do not want to stop booting for any failures here */
617 int ft_board_setup(void *fdt
, bd_t
*bd
)
619 const char *slave_path
, *enet_name
;
620 int enetnode
, slavenode
, phynode
;
621 struct udevice
*ethdev
;
627 /* phy address fixup needed only on beagle bone family */
628 if (!board_is_beaglebonex())
631 for (i
= 0; i
< MAX_CPSW_SLAVES
; i
++) {
632 sprintf(alias
, "ethernet%d", i
);
634 slave_path
= fdt_get_alias(fdt
, alias
);
638 slavenode
= fdt_path_offset(fdt
, slave_path
);
642 enetnode
= fdt_parent_offset(fdt
, slavenode
);
643 enet_name
= fdt_get_name(fdt
, enetnode
, NULL
);
645 ethdev
= eth_get_dev_by_name(enet_name
);
649 phy_addr
= cpsw_get_slave_phy_addr(ethdev
, i
);
651 /* check for phy_id as well as phy-handle properties */
652 ret
= fdtdec_get_int_array_count(fdt
, slavenode
, "phy_id",
655 if (phy_id
[1] != phy_addr
) {
656 printf("fixing up phy_id for %s, old: %d, new: %d\n",
657 alias
, phy_id
[1], phy_addr
);
659 phy_id
[0] = cpu_to_fdt32(phy_id
[0]);
660 phy_id
[1] = cpu_to_fdt32(phy_addr
);
661 do_fixup_by_path(fdt
, slave_path
, "phy_id",
662 phy_id
, sizeof(phy_id
), 0);
665 phynode
= fdtdec_lookup_phandle(fdt
, slavenode
,
670 ret
= fdtdec_get_int(fdt
, phynode
, "reg", -ENOENT
);
674 if (ret
!= phy_addr
) {
675 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
676 alias
, ret
, phy_addr
);
678 fdt_setprop_u32(fdt
, phynode
, "reg",
679 cpu_to_fdt32(phy_addr
));
690 * Basic board specific setup. Pinmux has been handled already.
694 #if defined(CONFIG_HW_WATCHDOG)
698 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
699 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
703 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
704 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
705 if (board_is_icev2()) {
709 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL
);
710 /* Make J19 status available on GPIO1_26 */
711 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL
);
713 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL
);
715 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
716 * jumpers near the port. Read the jumper value and set
717 * the pinmux, external mux and PHY clock accordingly.
718 * As jumper line is overridden by PHY RX_DV pin immediately
719 * after bootstrap (power-up/reset), we need to sample
720 * it during PHY reset using GPIO rising edge detection.
722 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET
);
723 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
724 reg
= readl(GPIO0_RISINGDETECT
) | BIT(11);
725 writel(reg
, GPIO0_RISINGDETECT
);
726 reg
= readl(GPIO1_RISINGDETECT
) | BIT(26);
727 writel(reg
, GPIO1_RISINGDETECT
);
728 /* Reset PHYs to capture the Jumper setting */
729 gpio_set_value(GPIO_PHY_RESET
, 0);
730 udelay(2); /* PHY datasheet states 1uS min. */
731 gpio_set_value(GPIO_PHY_RESET
, 1);
733 reg
= readl(GPIO0_IRQSTATUSRAW
) & BIT(11);
735 writel(reg
, GPIO0_IRQSTATUS1
); /* clear irq */
737 printf("ETH0, CPSW\n");
740 printf("ETH0, PRU\n");
741 cdce913_data
.pdiv3
= 4; /* 25MHz PHY clk */
744 reg
= readl(GPIO1_IRQSTATUSRAW
) & BIT(26);
746 writel(reg
, GPIO1_IRQSTATUS1
); /* clear irq */
748 printf("ETH1, CPSW\n");
749 gpio_set_value(GPIO_MUX_MII_CTRL
, 1);
752 printf("ETH1, PRU\n");
753 cdce913_data
.pdiv2
= 4; /* 25MHz PHY clk */
756 /* disable rising edge IRQs */
757 reg
= readl(GPIO0_RISINGDETECT
) & ~BIT(11);
758 writel(reg
, GPIO0_RISINGDETECT
);
759 reg
= readl(GPIO1_RISINGDETECT
) & ~BIT(26);
760 writel(reg
, GPIO1_RISINGDETECT
);
762 rv
= setup_clock_synthesizer(&cdce913_data
);
764 printf("Clock synthesizer setup failed %d\n", rv
);
769 gpio_set_value(GPIO_PHY_RESET
, 0);
770 udelay(2); /* PHY datasheet states 1uS min. */
771 gpio_set_value(GPIO_PHY_RESET
, 1);
778 #ifdef CONFIG_BOARD_LATE_INIT
779 int board_late_init(void)
781 #if !defined(CONFIG_SPL_BUILD)
783 uint32_t mac_hi
, mac_lo
;
786 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
789 if (board_is_bone_lt()) {
790 /* BeagleBoard.org BeagleBone Black Wireless: */
791 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
794 /* SeeedStudio BeagleBone Green Wireless */
795 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
798 /* BeagleBoard.org BeagleBone Blue */
799 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
808 set_board_info_env(name
);
811 * Default FIT boot on HS devices. Non FIT images are not allowed
814 if (get_device_type() == HS_DEVICE
)
815 env_set("boot_fit", "1");
818 #if !defined(CONFIG_SPL_BUILD)
819 /* try reading mac address from efuse */
820 mac_lo
= readl(&cdev
->macid0l
);
821 mac_hi
= readl(&cdev
->macid0h
);
822 mac_addr
[0] = mac_hi
& 0xFF;
823 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
824 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
825 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
826 mac_addr
[4] = mac_lo
& 0xFF;
827 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
829 if (!env_get("ethaddr")) {
830 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
832 if (is_valid_ethaddr(mac_addr
))
833 eth_env_set_enetaddr("ethaddr", mac_addr
);
836 mac_lo
= readl(&cdev
->macid1l
);
837 mac_hi
= readl(&cdev
->macid1h
);
838 mac_addr
[0] = mac_hi
& 0xFF;
839 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
840 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
841 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
842 mac_addr
[4] = mac_lo
& 0xFF;
843 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
845 if (!env_get("eth1addr")) {
846 if (is_valid_ethaddr(mac_addr
))
847 eth_env_set_enetaddr("eth1addr", mac_addr
);
851 if (!env_get("serial#")) {
852 char *board_serial
= env_get("board_serial");
853 char *ethaddr
= env_get("ethaddr");
855 if (!board_serial
|| !strncmp(board_serial
, "unknown", 7))
856 env_set("serial#", ethaddr
);
858 env_set("serial#", board_serial
);
865 #ifndef CONFIG_DM_ETH
867 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
868 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
869 static void cpsw_control(int enabled
)
871 /* VTP can be added here */
876 static struct cpsw_slave_data cpsw_slaves
[] = {
878 .slave_reg_ofs
= 0x208,
879 .sliver_reg_ofs
= 0xd80,
883 .slave_reg_ofs
= 0x308,
884 .sliver_reg_ofs
= 0xdc0,
889 static struct cpsw_platform_data cpsw_data
= {
890 .mdio_base
= CPSW_MDIO_BASE
,
891 .cpsw_base
= CPSW_BASE
,
894 .cpdma_reg_ofs
= 0x800,
896 .slave_data
= cpsw_slaves
,
897 .ale_reg_ofs
= 0xd00,
899 .host_port_reg_ofs
= 0x108,
900 .hw_stats_reg_ofs
= 0x900,
901 .bd_ram_ofs
= 0x2000,
902 .mac_control
= (1 << 5),
903 .control
= cpsw_control
,
905 .version
= CPSW_CTRL_VERSION_2
,
909 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
910 defined(CONFIG_SPL_BUILD)) || \
911 ((defined(CONFIG_DRIVER_TI_CPSW) || \
912 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
913 !defined(CONFIG_SPL_BUILD))
916 * This function will:
917 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
919 * Perform fixups to the PHY present on certain boards. We only need this
921 * - SPL with either CPSW or USB ethernet support
922 * - Full U-Boot, with either CPSW or USB ethernet
923 * Build in only these cases to avoid warnings about unused variables
924 * when we build an SPL that has neither option but full U-Boot will.
926 int board_eth_init(bd_t
*bis
)
929 #if defined(CONFIG_USB_ETHER) && \
930 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
932 uint32_t mac_hi
, mac_lo
;
935 * use efuse mac address for USB ethernet as we know that
936 * both CPSW and USB ethernet will never be active at the same time
938 mac_lo
= readl(&cdev
->macid0l
);
939 mac_hi
= readl(&cdev
->macid0h
);
940 mac_addr
[0] = mac_hi
& 0xFF;
941 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
942 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
943 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
944 mac_addr
[4] = mac_lo
& 0xFF;
945 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
949 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
950 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
952 #ifdef CONFIG_DRIVER_TI_CPSW
953 if (board_is_bone() || board_is_bone_lt() || board_is_bben() ||
955 writel(MII_MODE_ENABLE
, &cdev
->miisel
);
956 cpsw_slaves
[0].phy_if
= cpsw_slaves
[1].phy_if
=
957 PHY_INTERFACE_MODE_MII
;
958 } else if (board_is_icev2()) {
959 writel(RMII_MODE_ENABLE
| RMII_CHIPCKL_ENABLE
, &cdev
->miisel
);
960 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RMII
;
961 cpsw_slaves
[1].phy_if
= PHY_INTERFACE_MODE_RMII
;
962 cpsw_slaves
[0].phy_addr
= 1;
963 cpsw_slaves
[1].phy_addr
= 3;
965 writel((RGMII_MODE_ENABLE
| RGMII_INT_DELAY
), &cdev
->miisel
);
966 cpsw_slaves
[0].phy_if
= cpsw_slaves
[1].phy_if
=
967 PHY_INTERFACE_MODE_RGMII
;
970 rv
= cpsw_register(&cpsw_data
);
972 printf("Error %d registering CPSW switch\n", rv
);
979 * CPSW RGMII Internal Delay Mode is not supported in all PVT
980 * operating points. So we must set the TX clock delay feature
981 * in the AR8051 PHY. Since we only support a single ethernet
982 * device in U-Boot, we only do this for the first instance.
984 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
985 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
986 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
987 #define AR8051_RGMII_TX_CLK_DLY 0x100
989 if (board_is_evm_sk() || board_is_gp_evm() || board_is_bben()) {
991 devname
= miiphy_get_current_dev();
993 miiphy_write(devname
, 0x0, AR8051_PHY_DEBUG_ADDR_REG
,
994 AR8051_DEBUG_RGMII_CLK_DLY_REG
);
995 miiphy_write(devname
, 0x0, AR8051_PHY_DEBUG_DATA_REG
,
996 AR8051_RGMII_TX_CLK_DLY
);
999 #if defined(CONFIG_USB_ETHER) && \
1000 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
1001 if (is_valid_ethaddr(mac_addr
))
1002 eth_env_set_enetaddr("usbnet_devaddr", mac_addr
);
1004 rv
= usb_eth_initialize(bis
);
1006 printf("Error %d registering USB_ETHER\n", rv
);
1014 #endif /* CONFIG_DM_ETH */
1016 #ifdef CONFIG_SPL_LOAD_FIT
1017 int board_fit_config_name_match(const char *name
)
1019 if (board_is_gp_evm() && !strcmp(name
, "am335x-evm"))
1021 else if (board_is_bone() && !strcmp(name
, "am335x-bone"))
1023 else if (board_is_bone_lt() && !strcmp(name
, "am335x-boneblack"))
1025 else if (board_is_pb() && !strcmp(name
, "am335x-pocketbeagle"))
1027 else if (board_is_evm_sk() && !strcmp(name
, "am335x-evmsk"))
1029 else if (board_is_bbg1() && !strcmp(name
, "am335x-bonegreen"))
1031 else if (board_is_icev2() && !strcmp(name
, "am335x-icev2"))
1038 #ifdef CONFIG_TI_SECURE_DEVICE
1039 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
1041 secure_boot_verify_image(p_image
, p_size
);
1045 #if !CONFIG_IS_ENABLED(OF_CONTROL)
1046 static const struct omap_hsmmc_plat am335x_mmc0_platdata
= {
1047 .base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
,
1048 .cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
| MMC_MODE_4BIT
,
1049 .cfg
.f_min
= 400000,
1050 .cfg
.f_max
= 52000000,
1051 .cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
,
1052 .cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
,
1055 U_BOOT_DEVICE(am335x_mmc0
) = {
1056 .name
= "omap_hsmmc",
1057 .platdata
= &am335x_mmc0_platdata
,
1060 static const struct omap_hsmmc_plat am335x_mmc1_platdata
= {
1061 .base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
,
1062 .cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
| MMC_MODE_8BIT
,
1063 .cfg
.f_min
= 400000,
1064 .cfg
.f_max
= 52000000,
1065 .cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
,
1066 .cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
,
1069 U_BOOT_DEVICE(am335x_mmc1
) = {
1070 .name
= "omap_hsmmc",
1071 .platdata
= &am335x_mmc1_platdata
,