board/ti/am335x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM335X based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <errno.h>
  14 #include <init.h>
  15 #include <spl.h>
  16 #include <serial.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/omap.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/clk_synthesizer.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/arch/mmc_host_def.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/mem.h>
  27 #include <asm/io.h>
  28 #include <asm/emif.h>
  29 #include <asm/gpio.h>
  30 #include <asm/omap_common.h>
  31 #include <asm/omap_sec_common.h>
  32 #include <asm/omap_mmc.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36 #include <power/tps65217.h>
  37 #include <power/tps65910.h>
  38 #include <env_internal.h>
  39 #include <watchdog.h>
  40 #include "../common/board_detect.h"
  41 #include "board.h"
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 /* GPIO that controls power to DDR on EVM-SK */
  46 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  47 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  48 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  49 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  50 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  51 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  52 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  53 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  54 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  55
  56 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  57
  58 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  59 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  60
  61 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  62 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  63
  64 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  65 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  66
  67 /*
  68  * Read header information from EEPROM into global structure.
  69  */
  70 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  71 void do_board_detect(void)
  72 {
  73         enable_i2c0_pin_mux();
  74 #ifndef CONFIG_DM_I2C
  75         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  76 #endif
  77         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  78                                  CONFIG_EEPROM_CHIP_ADDRESS))
  79                 printf("ti_i2c_eeprom_init failed\n");
  80 }
  81 #endif
  82
  83 #ifndef CONFIG_DM_SERIAL
  84 struct serial_device *default_serial_console(void)
  85 {
  86         if (board_is_icev2())
  87                 return &eserial4_device;
  88         else
  89                 return &eserial1_device;
  90 }
  91 #endif
  92
  93 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  94 static const struct ddr_data ddr2_data = {
  95         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  96         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  97         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  98 };
  99
 100 static const struct cmd_control ddr2_cmd_ctrl_data = {
 101         .cmd0csratio = MT47H128M16RT25E_RATIO,
 102
 103         .cmd1csratio = MT47H128M16RT25E_RATIO,
 104
 105         .cmd2csratio = MT47H128M16RT25E_RATIO,
 106 };
 107
 108 static const struct emif_regs ddr2_emif_reg_data = {
 109         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 110         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 111         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 112         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 113         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 114         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 115 };
 116
 117 static const struct emif_regs ddr2_evm_emif_reg_data = {
 118         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 119         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 120         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 121         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 122         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 123         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 124         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 125 };
 126
 127 static const struct ddr_data ddr3_data = {
 128         .datardsratio0 = MT41J128MJT125_RD_DQS,
 129         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 130         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 131         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 132 };
 133
 134 static const struct ddr_data ddr3_beagleblack_data = {
 135         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 136         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 137         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 138         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 139 };
 140
 141 static const struct ddr_data ddr3_evm_data = {
 142         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 143         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 144         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 145         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 146 };
 147
 148 static const struct ddr_data ddr3_icev2_data = {
 149         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 150         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 151         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 152         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 153 };
 154
 155 static const struct cmd_control ddr3_cmd_ctrl_data = {
 156         .cmd0csratio = MT41J128MJT125_RATIO,
 157         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 158
 159         .cmd1csratio = MT41J128MJT125_RATIO,
 160         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 161
 162         .cmd2csratio = MT41J128MJT125_RATIO,
 163         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 164 };
 165
 166 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 167         .cmd0csratio = MT41K256M16HA125E_RATIO,
 168         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 169
 170         .cmd1csratio = MT41K256M16HA125E_RATIO,
 171         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 172
 173         .cmd2csratio = MT41K256M16HA125E_RATIO,
 174         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 175 };
 176
 177 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 178         .cmd0csratio = MT41J512M8RH125_RATIO,
 179         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 180
 181         .cmd1csratio = MT41J512M8RH125_RATIO,
 182         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 183
 184         .cmd2csratio = MT41J512M8RH125_RATIO,
 185         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 186 };
 187
 188 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 189         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 190         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 191
 192         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 193         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 194
 195         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 196         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 197 };
 198
 199 static struct emif_regs ddr3_emif_reg_data = {
 200         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 201         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 202         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 203         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 204         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 205         .zq_config = MT41J128MJT125_ZQ_CFG,
 206         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 207                                 PHY_EN_DYN_PWRDN,
 208 };
 209
 210 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 211         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 212         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 213         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 214         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 215         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 216         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 217         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 218         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 219 };
 220
 221 static struct emif_regs ddr3_evm_emif_reg_data = {
 222         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 223         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 224         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 225         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 226         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 227         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 228         .zq_config = MT41J512M8RH125_ZQ_CFG,
 229         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 230                                 PHY_EN_DYN_PWRDN,
 231 };
 232
 233 static struct emif_regs ddr3_icev2_emif_reg_data = {
 234         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 235         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 236         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 237         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 238         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 239         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 240         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 241                                 PHY_EN_DYN_PWRDN,
 242 };
 243
 244 #ifdef CONFIG_SPL_OS_BOOT
 245 int spl_start_uboot(void)
 246 {
 247 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 248         /* break into full u-boot on 'c' */
 249         if (serial_tstc() && serial_getc() == 'c')
 250                 return 1;
 251 #endif
 252
 253 #ifdef CONFIG_SPL_ENV_SUPPORT
 254         env_init();
 255         env_load();
 256         if (env_get_yesno("boot_os") != 1)
 257                 return 1;
 258 #endif
 259
 260         return 0;
 261 }
 262 #endif
 263
 264 const struct dpll_params *get_dpll_ddr_params(void)
 265 {
 266         int ind = get_sys_clk_index();
 267
 268         if (board_is_evm_sk())
 269                 return &dpll_ddr3_303MHz[ind];
 270         else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
 271                 return &dpll_ddr3_400MHz[ind];
 272         else if (board_is_evm_15_or_later())
 273                 return &dpll_ddr3_303MHz[ind];
 274         else
 275                 return &dpll_ddr2_266MHz[ind];
 276 }
 277
 278 static u8 bone_not_connected_to_ac_power(void)
 279 {
 280         if (board_is_bone()) {
 281                 uchar pmic_status_reg;
 282                 if (tps65217_reg_read(TPS65217_STATUS,
 283                                       &pmic_status_reg))
 284                         return 1;
 285                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 286                         puts("No AC power, switching to default OPP\n");
 287                         return 1;
 288                 }
 289         }
 290         return 0;
 291 }
 292
 293 const struct dpll_params *get_dpll_mpu_params(void)
 294 {
 295         int ind = get_sys_clk_index();
 296         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 297
 298         if (bone_not_connected_to_ac_power())
 299                 freq = MPUPLL_M_600;
 300
 301         if (board_is_pb() || board_is_bone_lt())
 302                 freq = MPUPLL_M_1000;
 303
 304         switch (freq) {
 305         case MPUPLL_M_1000:
 306                 return &dpll_mpu_opp[ind][5];
 307         case MPUPLL_M_800:
 308                 return &dpll_mpu_opp[ind][4];
 309         case MPUPLL_M_720:
 310                 return &dpll_mpu_opp[ind][3];
 311         case MPUPLL_M_600:
 312                 return &dpll_mpu_opp[ind][2];
 313         case MPUPLL_M_500:
 314                 return &dpll_mpu_opp100;
 315         case MPUPLL_M_300:
 316                 return &dpll_mpu_opp[ind][0];
 317         }
 318
 319         return &dpll_mpu_opp[ind][0];
 320 }
 321
 322 static void scale_vcores_bone(int freq)
 323 {
 324         int usb_cur_lim, mpu_vdd;
 325
 326         /*
 327          * Only perform PMIC configurations if board rev > A1
 328          * on Beaglebone White
 329          */
 330         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 331                 return;
 332
 333 #ifndef CONFIG_DM_I2C
 334         if (i2c_probe(TPS65217_CHIP_PM))
 335                 return;
 336 #else
 337         if (power_tps65217_init(0))
 338                 return;
 339 #endif
 340
 341
 342         /*
 343          * On Beaglebone White we need to ensure we have AC power
 344          * before increasing the frequency.
 345          */
 346         if (bone_not_connected_to_ac_power())
 347                 freq = MPUPLL_M_600;
 348
 349         /*
 350          * Override what we have detected since we know if we have
 351          * a Beaglebone Black it supports 1GHz.
 352          */
 353         if (board_is_pb() || board_is_bone_lt())
 354                 freq = MPUPLL_M_1000;
 355
 356         switch (freq) {
 357         case MPUPLL_M_1000:
 358                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 359                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 360                 break;
 361         case MPUPLL_M_800:
 362                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 363                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 364                 break;
 365         case MPUPLL_M_720:
 366                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 367                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 368                 break;
 369         case MPUPLL_M_600:
 370         case MPUPLL_M_500:
 371         case MPUPLL_M_300:
 372         default:
 373                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 374                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 375                 break;
 376         }
 377
 378         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 379                                TPS65217_POWER_PATH,
 380                                usb_cur_lim,
 381                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 382                 puts("tps65217_reg_write failure\n");
 383
 384         /* Set DCDC3 (CORE) voltage to 1.10V */
 385         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 386                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
 387                 puts("tps65217_voltage_update failure\n");
 388                 return;
 389         }
 390
 391         /* Set DCDC2 (MPU) voltage */
 392         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 393                 puts("tps65217_voltage_update failure\n");
 394                 return;
 395         }
 396
 397         /*
 398          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 399          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 400          */
 401         if (board_is_bone()) {
 402                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 403                                        TPS65217_DEFLS1,
 404                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 405                                        TPS65217_LDO_MASK))
 406                         puts("tps65217_reg_write failure\n");
 407         } else {
 408                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 409                                        TPS65217_DEFLS1,
 410                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
 411                                        TPS65217_LDO_MASK))
 412                         puts("tps65217_reg_write failure\n");
 413         }
 414
 415         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 416                                TPS65217_DEFLS2,
 417                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 418                                TPS65217_LDO_MASK))
 419                 puts("tps65217_reg_write failure\n");
 420 }
 421
 422 void scale_vcores_generic(int freq)
 423 {
 424         int sil_rev, mpu_vdd;
 425
 426         /*
 427          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 428          * MPU frequencies we support we use a CORE voltage of
 429          * 1.10V.  For MPU voltage we need to switch based on
 430          * the frequency we are running at.
 431          */
 432 #ifndef CONFIG_DM_I2C
 433         if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 434                 return;
 435 #else
 436         if (power_tps65910_init(0))
 437                 return;
 438 #endif
 439         /*
 440          * Depending on MPU clock and PG we will need a different
 441          * VDD to drive at that speed.
 442          */
 443         sil_rev = readl(&cdev->deviceid) >> 28;
 444         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 445
 446         /* Tell the TPS65910 to use i2c */
 447         tps65910_set_i2c_control();
 448
 449         /* First update MPU voltage. */
 450         if (tps65910_voltage_update(MPU, mpu_vdd))
 451                 return;
 452
 453         /* Second, update the CORE voltage. */
 454         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 455                 return;
 456
 457 }
 458
 459 void gpi2c_init(void)
 460 {
 461         /* When needed to be invoked prior to BSS initialization */
 462         static bool first_time = true;
 463
 464         if (first_time) {
 465                 enable_i2c0_pin_mux();
 466 #ifndef CONFIG_DM_I2C
 467                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 468                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 469 #endif
 470                 first_time = false;
 471         }
 472 }
 473
 474 void scale_vcores(void)
 475 {
 476         int freq;
 477
 478         gpi2c_init();
 479         freq = am335x_get_efuse_mpu_max_freq(cdev);
 480
 481         if (board_is_beaglebonex())
 482                 scale_vcores_bone(freq);
 483         else
 484                 scale_vcores_generic(freq);
 485 }
 486
 487 void set_uart_mux_conf(void)
 488 {
 489 #if CONFIG_CONS_INDEX == 1
 490         enable_uart0_pin_mux();
 491 #elif CONFIG_CONS_INDEX == 2
 492         enable_uart1_pin_mux();
 493 #elif CONFIG_CONS_INDEX == 3
 494         enable_uart2_pin_mux();
 495 #elif CONFIG_CONS_INDEX == 4
 496         enable_uart3_pin_mux();
 497 #elif CONFIG_CONS_INDEX == 5
 498         enable_uart4_pin_mux();
 499 #elif CONFIG_CONS_INDEX == 6
 500         enable_uart5_pin_mux();
 501 #endif
 502 }
 503
 504 void set_mux_conf_regs(void)
 505 {
 506         enable_board_pin_mux();
 507 }
 508
 509 const struct ctrl_ioregs ioregs_evmsk = {
 510         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 511         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 512         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 513         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 514         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 515 };
 516
 517 const struct ctrl_ioregs ioregs_bonelt = {
 518         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 519         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 520         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 521         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 522         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 523 };
 524
 525 const struct ctrl_ioregs ioregs_evm15 = {
 526         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 527         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 528         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 529         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 530         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 531 };
 532
 533 const struct ctrl_ioregs ioregs = {
 534         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 535         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 536         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 537         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 538         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 539 };
 540
 541 void sdram_init(void)
 542 {
 543         if (board_is_evm_sk()) {
 544                 /*
 545                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 546                  * This is safe enough to do on older revs.
 547                  */
 548                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 549                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 550         }
 551
 552         if (board_is_icev2()) {
 553                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 554                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 555         }
 556
 557         if (board_is_evm_sk())
 558                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 559                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 560         else if (board_is_pb() || board_is_bone_lt())
 561                 config_ddr(400, &ioregs_bonelt,
 562                            &ddr3_beagleblack_data,
 563                            &ddr3_beagleblack_cmd_ctrl_data,
 564                            &ddr3_beagleblack_emif_reg_data, 0);
 565         else if (board_is_evm_15_or_later())
 566                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 567                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 568         else if (board_is_icev2())
 569                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 570                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 571                            0);
 572         else if (board_is_gp_evm())
 573                 config_ddr(266, &ioregs, &ddr2_data,
 574                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 575         else
 576                 config_ddr(266, &ioregs, &ddr2_data,
 577                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 578 }
 579 #endif
 580
 581 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 582         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
 583 static void request_and_set_gpio(int gpio, char *name, int val)
 584 {
 585         int ret;
 586
 587         ret = gpio_request(gpio, name);
 588         if (ret < 0) {
 589                 printf("%s: Unable to request %s\n", __func__, name);
 590                 return;
 591         }
 592
 593         ret = gpio_direction_output(gpio, 0);
 594         if (ret < 0) {
 595                 printf("%s: Unable to set %s  as output\n", __func__, name);
 596                 goto err_free_gpio;
 597         }
 598
 599         gpio_set_value(gpio, val);
 600
 601         return;
 602
 603 err_free_gpio:
 604         gpio_free(gpio);
 605 }
 606
 607 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 608 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 609
 610 /**
 611  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 612  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 613  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 614  * give 50MHz output for Eth0 and 1.
 615  */
 616 static struct clk_synth cdce913_data = {
 617         .id = 0x81,
 618         .capacitor = 0x90,
 619         .mux = 0x6d,
 620         .pdiv2 = 0x2,
 621         .pdiv3 = 0x2,
 622 };
 623 #endif
 624
 625 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
 626         defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
 627
 628 #define MAX_CPSW_SLAVES 2
 629
 630 /* At the moment, we do not want to stop booting for any failures here */
 631 int ft_board_setup(void *fdt, bd_t *bd)
 632 {
 633         const char *slave_path, *enet_name;
 634         int enetnode, slavenode, phynode;
 635         struct udevice *ethdev;
 636         char alias[16];
 637         u32 phy_id[2];
 638         int phy_addr;
 639         int i, ret;
 640
 641         /* phy address fixup needed only on beagle bone family */
 642         if (!board_is_beaglebonex())
 643                 goto done;
 644
 645         for (i = 0; i < MAX_CPSW_SLAVES; i++) {
 646                 sprintf(alias, "ethernet%d", i);
 647
 648                 slave_path = fdt_get_alias(fdt, alias);
 649                 if (!slave_path)
 650                         continue;
 651
 652                 slavenode = fdt_path_offset(fdt, slave_path);
 653                 if (slavenode < 0)
 654                         continue;
 655
 656                 enetnode = fdt_parent_offset(fdt, slavenode);
 657                 enet_name = fdt_get_name(fdt, enetnode, NULL);
 658
 659                 ethdev = eth_get_dev_by_name(enet_name);
 660                 if (!ethdev)
 661                         continue;
 662
 663                 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
 664
 665                 /* check for phy_id as well as phy-handle properties */
 666                 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
 667                                                  phy_id, 2);
 668                 if (ret == 2) {
 669                         if (phy_id[1] != phy_addr) {
 670                                 printf("fixing up phy_id for %s, old: %d, new: %d\n",
 671                                        alias, phy_id[1], phy_addr);
 672
 673                                 phy_id[0] = cpu_to_fdt32(phy_id[0]);
 674                                 phy_id[1] = cpu_to_fdt32(phy_addr);
 675                                 do_fixup_by_path(fdt, slave_path, "phy_id",
 676                                                  phy_id, sizeof(phy_id), 0);
 677                         }
 678                 } else {
 679                         phynode = fdtdec_lookup_phandle(fdt, slavenode,
 680                                                         "phy-handle");
 681                         if (phynode < 0)
 682                                 continue;
 683
 684                         ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
 685                         if (ret < 0)
 686                                 continue;
 687
 688                         if (ret != phy_addr) {
 689                                 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
 690                                        alias, ret, phy_addr);
 691
 692                                 fdt_setprop_u32(fdt, phynode, "reg",
 693                                                 cpu_to_fdt32(phy_addr));
 694                         }
 695                 }
 696         }
 697
 698 done:
 699         return 0;
 700 }
 701 #endif
 702
 703 /*
 704  * Basic board specific setup.  Pinmux has been handled already.
 705  */
 706 int board_init(void)
 707 {
 708 #if defined(CONFIG_HW_WATCHDOG)
 709         hw_watchdog_init();
 710 #endif
 711
 712         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 713 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 714         gpmc_init();
 715 #endif
 716
 717 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 718         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
 719         if (board_is_icev2()) {
 720                 int rv;
 721                 u32 reg;
 722
 723                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 724                 /* Make J19 status available on GPIO1_26 */
 725                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 726
 727                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 728                 /*
 729                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 730                  * jumpers near the port. Read the jumper value and set
 731                  * the pinmux, external mux and PHY clock accordingly.
 732                  * As jumper line is overridden by PHY RX_DV pin immediately
 733                  * after bootstrap (power-up/reset), we need to sample
 734                  * it during PHY reset using GPIO rising edge detection.
 735                  */
 736                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 737                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 738                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 739                 writel(reg, GPIO0_RISINGDETECT);
 740                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 741                 writel(reg, GPIO1_RISINGDETECT);
 742                 /* Reset PHYs to capture the Jumper setting */
 743                 gpio_set_value(GPIO_PHY_RESET, 0);
 744                 udelay(2);      /* PHY datasheet states 1uS min. */
 745                 gpio_set_value(GPIO_PHY_RESET, 1);
 746
 747                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 748                 if (reg) {
 749                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 750                         /* RMII mode */
 751                         printf("ETH0, CPSW\n");
 752                 } else {
 753                         /* MII mode */
 754                         printf("ETH0, PRU\n");
 755                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 756                 }
 757
 758                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 759                 if (reg) {
 760                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 761                         /* RMII mode */
 762                         printf("ETH1, CPSW\n");
 763                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 764                 } else {
 765                         /* MII mode */
 766                         printf("ETH1, PRU\n");
 767                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 768                 }
 769
 770                 /* disable rising edge IRQs */
 771                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 772                 writel(reg, GPIO0_RISINGDETECT);
 773                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 774                 writel(reg, GPIO1_RISINGDETECT);
 775
 776                 rv = setup_clock_synthesizer(&cdce913_data);
 777                 if (rv) {
 778                         printf("Clock synthesizer setup failed %d\n", rv);
 779                         return rv;
 780                 }
 781
 782                 /* reset PHYs */
 783                 gpio_set_value(GPIO_PHY_RESET, 0);
 784                 udelay(2);      /* PHY datasheet states 1uS min. */
 785                 gpio_set_value(GPIO_PHY_RESET, 1);
 786         }
 787 #endif
 788
 789         return 0;
 790 }
 791
 792 #ifdef CONFIG_BOARD_LATE_INIT
 793 int board_late_init(void)
 794 {
 795         struct udevice *dev;
 796 #if !defined(CONFIG_SPL_BUILD)
 797         uint8_t mac_addr[6];
 798         uint32_t mac_hi, mac_lo;
 799 #endif
 800
 801 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 802         char *name = NULL;
 803
 804         if (board_is_bone_lt()) {
 805                 /* BeagleBoard.org BeagleBone Black Wireless: */
 806                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 807                         name = "BBBW";
 808                 }
 809                 /* SeeedStudio BeagleBone Green Wireless */
 810                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 811                         name = "BBGW";
 812                 }
 813                 /* BeagleBoard.org BeagleBone Blue */
 814                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 815                         name = "BBBL";
 816                 }
 817         }
 818
 819         if (board_is_bbg1())
 820                 name = "BBG1";
 821         if (board_is_bben())
 822                 name = "BBEN";
 823         set_board_info_env(name);
 824
 825         /*
 826          * Default FIT boot on HS devices. Non FIT images are not allowed
 827          * on HS devices.
 828          */
 829         if (get_device_type() == HS_DEVICE)
 830                 env_set("boot_fit", "1");
 831 #endif
 832
 833 #if !defined(CONFIG_SPL_BUILD)
 834         /* try reading mac address from efuse */
 835         mac_lo = readl(&cdev->macid0l);
 836         mac_hi = readl(&cdev->macid0h);
 837         mac_addr[0] = mac_hi & 0xFF;
 838         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 839         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 840         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 841         mac_addr[4] = mac_lo & 0xFF;
 842         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 843
 844         if (!env_get("ethaddr")) {
 845                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 846
 847                 if (is_valid_ethaddr(mac_addr))
 848                         eth_env_set_enetaddr("ethaddr", mac_addr);
 849         }
 850
 851         mac_lo = readl(&cdev->macid1l);
 852         mac_hi = readl(&cdev->macid1h);
 853         mac_addr[0] = mac_hi & 0xFF;
 854         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 855         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 856         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 857         mac_addr[4] = mac_lo & 0xFF;
 858         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 859
 860         if (!env_get("eth1addr")) {
 861                 if (is_valid_ethaddr(mac_addr))
 862                         eth_env_set_enetaddr("eth1addr", mac_addr);
 863         }
 864 #endif
 865
 866         if (!env_get("serial#")) {
 867                 char *board_serial = env_get("board_serial");
 868                 char *ethaddr = env_get("ethaddr");
 869
 870                 if (!board_serial || !strncmp(board_serial, "unknown", 7))
 871                         env_set("serial#", ethaddr);
 872                 else
 873                         env_set("serial#", board_serial);
 874         }
 875
 876         /* Just probe the potentially supported cdce913 device */
 877         uclass_get_device(UCLASS_CLK, 0, &dev);
 878
 879         return 0;
 880 }
 881 #endif
 882
 883 /* CPSW platdata */
 884 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 885 struct cpsw_slave_data slave_data[] = {
 886         {
 887                 .slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
 888                 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
 889                 .phy_addr       = 0,
 890         },
 891         {
 892                 .slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
 893                 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
 894                 .phy_addr       = 1,
 895         },
 896 };
 897
 898 struct cpsw_platform_data am335_eth_data = {
 899         .cpsw_base              = CPSW_BASE,
 900         .version                = CPSW_CTRL_VERSION_2,
 901         .bd_ram_ofs             = CPSW_BD_OFFSET,
 902         .ale_reg_ofs            = CPSW_ALE_OFFSET,
 903         .cpdma_reg_ofs          = CPSW_CPDMA_OFFSET,
 904         .mdio_div               = CPSW_MDIO_DIV,
 905         .host_port_reg_ofs      = CPSW_HOST_PORT_OFFSET,
 906         .channels               = 8,
 907         .slaves                 = 2,
 908         .slave_data             = slave_data,
 909         .ale_entries            = 1024,
 910         .bd_ram_ofs             = 0x2000,
 911         .mac_control            = 0x20,
 912         .active_slave           = 0,
 913         .mdio_base              = 0x4a101000,
 914         .gmii_sel               = 0x44e10650,
 915         .phy_sel_compat         = "ti,am3352-cpsw-phy-sel",
 916         .syscon_addr            = 0x44e10630,
 917         .macid_sel_compat       = "cpsw,am33xx",
 918 };
 919
 920 struct eth_pdata cpsw_pdata = {
 921         .iobase = 0x4a100000,
 922         .phy_interface = 0,
 923         .priv_pdata = &am335_eth_data,
 924 };
 925
 926 U_BOOT_DEVICE(am335x_eth) = {
 927         .name = "eth_cpsw",
 928         .platdata = &cpsw_pdata,
 929 };
 930 #endif
 931
 932 #ifdef CONFIG_SPL_LOAD_FIT
 933 int board_fit_config_name_match(const char *name)
 934 {
 935         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 936                 return 0;
 937         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 938                 return 0;
 939         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 940                 return 0;
 941         else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
 942                 return 0;
 943         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 944                 return 0;
 945         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 946                 return 0;
 947         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 948                 return 0;
 949         else
 950                 return -1;
 951 }
 952 #endif
 953
 954 #ifdef CONFIG_TI_SECURE_DEVICE
 955 void board_fit_image_post_process(void **p_image, size_t *p_size)
 956 {
 957         secure_boot_verify_image(p_image, p_size);
 958 }
 959 #endif
 960
 961 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 962 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
 963         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 964         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 965         .cfg.f_min = 400000,
 966         .cfg.f_max = 52000000,
 967         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 968         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 969 };
 970
 971 U_BOOT_DEVICE(am335x_mmc0) = {
 972         .name = "omap_hsmmc",
 973         .platdata = &am335x_mmc0_platdata,
 974 };
 975
 976 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
 977         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 978         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 979         .cfg.f_min = 400000,
 980         .cfg.f_max = 52000000,
 981         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 982         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 983 };
 984
 985 U_BOOT_DEVICE(am335x_mmc1) = {
 986         .name = "omap_hsmmc",
 987         .platdata = &am335x_mmc1_platdata,
 988 };
 989 #endif