1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for TI AM335X based boards
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/clk_synthesizer.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/mmc_host_def.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/mem.h>
33 #include <asm/omap_common.h>
34 #include <asm/omap_sec_common.h>
35 #include <asm/omap_mmc.h>
39 #include <power/tps65217.h>
40 #include <power/tps65910.h>
41 #include <env_internal.h>
43 #include "../common/board_detect.h"
46 DECLARE_GLOBAL_DATA_PTR
;
48 /* GPIO that controls power to DDR on EVM-SK */
49 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
50 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
51 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
52 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
53 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
54 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
55 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
56 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
57 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
59 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
61 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
62 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
64 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
65 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
67 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
68 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
71 * Read header information from EEPROM into global structure.
73 #ifdef CONFIG_TI_I2C_BOARD_DETECT
74 void do_board_detect(void)
76 enable_i2c0_pin_mux();
78 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
80 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
81 CONFIG_EEPROM_CHIP_ADDRESS
))
82 printf("ti_i2c_eeprom_init failed\n");
86 #ifndef CONFIG_DM_SERIAL
87 struct serial_device
*default_serial_console(void)
90 return &eserial4_device
;
92 return &eserial1_device
;
96 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
97 static const struct ddr_data ddr2_data
= {
98 .datardsratio0
= MT47H128M16RT25E_RD_DQS
,
99 .datafwsratio0
= MT47H128M16RT25E_PHY_FIFO_WE
,
100 .datawrsratio0
= MT47H128M16RT25E_PHY_WR_DATA
,
103 static const struct cmd_control ddr2_cmd_ctrl_data
= {
104 .cmd0csratio
= MT47H128M16RT25E_RATIO
,
106 .cmd1csratio
= MT47H128M16RT25E_RATIO
,
108 .cmd2csratio
= MT47H128M16RT25E_RATIO
,
111 static const struct emif_regs ddr2_emif_reg_data
= {
112 .sdram_config
= MT47H128M16RT25E_EMIF_SDCFG
,
113 .ref_ctrl
= MT47H128M16RT25E_EMIF_SDREF
,
114 .sdram_tim1
= MT47H128M16RT25E_EMIF_TIM1
,
115 .sdram_tim2
= MT47H128M16RT25E_EMIF_TIM2
,
116 .sdram_tim3
= MT47H128M16RT25E_EMIF_TIM3
,
117 .emif_ddr_phy_ctlr_1
= MT47H128M16RT25E_EMIF_READ_LATENCY
,
120 static const struct emif_regs ddr2_evm_emif_reg_data
= {
121 .sdram_config
= MT47H128M16RT25E_EMIF_SDCFG
,
122 .ref_ctrl
= MT47H128M16RT25E_EMIF_SDREF
,
123 .sdram_tim1
= MT47H128M16RT25E_EMIF_TIM1
,
124 .sdram_tim2
= MT47H128M16RT25E_EMIF_TIM2
,
125 .sdram_tim3
= MT47H128M16RT25E_EMIF_TIM3
,
126 .ocp_config
= EMIF_OCP_CONFIG_AM335X_EVM
,
127 .emif_ddr_phy_ctlr_1
= MT47H128M16RT25E_EMIF_READ_LATENCY
,
130 static const struct ddr_data ddr3_data
= {
131 .datardsratio0
= MT41J128MJT125_RD_DQS
,
132 .datawdsratio0
= MT41J128MJT125_WR_DQS
,
133 .datafwsratio0
= MT41J128MJT125_PHY_FIFO_WE
,
134 .datawrsratio0
= MT41J128MJT125_PHY_WR_DATA
,
137 static const struct ddr_data ddr3_beagleblack_data
= {
138 .datardsratio0
= MT41K256M16HA125E_RD_DQS
,
139 .datawdsratio0
= MT41K256M16HA125E_WR_DQS
,
140 .datafwsratio0
= MT41K256M16HA125E_PHY_FIFO_WE
,
141 .datawrsratio0
= MT41K256M16HA125E_PHY_WR_DATA
,
144 static const struct ddr_data ddr3_evm_data
= {
145 .datardsratio0
= MT41J512M8RH125_RD_DQS
,
146 .datawdsratio0
= MT41J512M8RH125_WR_DQS
,
147 .datafwsratio0
= MT41J512M8RH125_PHY_FIFO_WE
,
148 .datawrsratio0
= MT41J512M8RH125_PHY_WR_DATA
,
151 static const struct ddr_data ddr3_icev2_data
= {
152 .datardsratio0
= MT41J128MJT125_RD_DQS_400MHz
,
153 .datawdsratio0
= MT41J128MJT125_WR_DQS_400MHz
,
154 .datafwsratio0
= MT41J128MJT125_PHY_FIFO_WE_400MHz
,
155 .datawrsratio0
= MT41J128MJT125_PHY_WR_DATA_400MHz
,
158 static const struct cmd_control ddr3_cmd_ctrl_data
= {
159 .cmd0csratio
= MT41J128MJT125_RATIO
,
160 .cmd0iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
162 .cmd1csratio
= MT41J128MJT125_RATIO
,
163 .cmd1iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
165 .cmd2csratio
= MT41J128MJT125_RATIO
,
166 .cmd2iclkout
= MT41J128MJT125_INVERT_CLKOUT
,
169 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data
= {
170 .cmd0csratio
= MT41K256M16HA125E_RATIO
,
171 .cmd0iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
173 .cmd1csratio
= MT41K256M16HA125E_RATIO
,
174 .cmd1iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
176 .cmd2csratio
= MT41K256M16HA125E_RATIO
,
177 .cmd2iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
180 static const struct cmd_control ddr3_evm_cmd_ctrl_data
= {
181 .cmd0csratio
= MT41J512M8RH125_RATIO
,
182 .cmd0iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
184 .cmd1csratio
= MT41J512M8RH125_RATIO
,
185 .cmd1iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
187 .cmd2csratio
= MT41J512M8RH125_RATIO
,
188 .cmd2iclkout
= MT41J512M8RH125_INVERT_CLKOUT
,
191 static const struct cmd_control ddr3_icev2_cmd_ctrl_data
= {
192 .cmd0csratio
= MT41J128MJT125_RATIO_400MHz
,
193 .cmd0iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
195 .cmd1csratio
= MT41J128MJT125_RATIO_400MHz
,
196 .cmd1iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
198 .cmd2csratio
= MT41J128MJT125_RATIO_400MHz
,
199 .cmd2iclkout
= MT41J128MJT125_INVERT_CLKOUT_400MHz
,
202 static struct emif_regs ddr3_emif_reg_data
= {
203 .sdram_config
= MT41J128MJT125_EMIF_SDCFG
,
204 .ref_ctrl
= MT41J128MJT125_EMIF_SDREF
,
205 .sdram_tim1
= MT41J128MJT125_EMIF_TIM1
,
206 .sdram_tim2
= MT41J128MJT125_EMIF_TIM2
,
207 .sdram_tim3
= MT41J128MJT125_EMIF_TIM3
,
208 .zq_config
= MT41J128MJT125_ZQ_CFG
,
209 .emif_ddr_phy_ctlr_1
= MT41J128MJT125_EMIF_READ_LATENCY
|
213 static struct emif_regs ddr3_beagleblack_emif_reg_data
= {
214 .sdram_config
= MT41K256M16HA125E_EMIF_SDCFG
,
215 .ref_ctrl
= MT41K256M16HA125E_EMIF_SDREF
,
216 .sdram_tim1
= MT41K256M16HA125E_EMIF_TIM1
,
217 .sdram_tim2
= MT41K256M16HA125E_EMIF_TIM2
,
218 .sdram_tim3
= MT41K256M16HA125E_EMIF_TIM3
,
219 .ocp_config
= EMIF_OCP_CONFIG_BEAGLEBONE_BLACK
,
220 .zq_config
= MT41K256M16HA125E_ZQ_CFG
,
221 .emif_ddr_phy_ctlr_1
= MT41K256M16HA125E_EMIF_READ_LATENCY
,
224 static struct emif_regs ddr3_evm_emif_reg_data
= {
225 .sdram_config
= MT41J512M8RH125_EMIF_SDCFG
,
226 .ref_ctrl
= MT41J512M8RH125_EMIF_SDREF
,
227 .sdram_tim1
= MT41J512M8RH125_EMIF_TIM1
,
228 .sdram_tim2
= MT41J512M8RH125_EMIF_TIM2
,
229 .sdram_tim3
= MT41J512M8RH125_EMIF_TIM3
,
230 .ocp_config
= EMIF_OCP_CONFIG_AM335X_EVM
,
231 .zq_config
= MT41J512M8RH125_ZQ_CFG
,
232 .emif_ddr_phy_ctlr_1
= MT41J512M8RH125_EMIF_READ_LATENCY
|
236 static struct emif_regs ddr3_icev2_emif_reg_data
= {
237 .sdram_config
= MT41J128MJT125_EMIF_SDCFG_400MHz
,
238 .ref_ctrl
= MT41J128MJT125_EMIF_SDREF_400MHz
,
239 .sdram_tim1
= MT41J128MJT125_EMIF_TIM1_400MHz
,
240 .sdram_tim2
= MT41J128MJT125_EMIF_TIM2_400MHz
,
241 .sdram_tim3
= MT41J128MJT125_EMIF_TIM3_400MHz
,
242 .zq_config
= MT41J128MJT125_ZQ_CFG_400MHz
,
243 .emif_ddr_phy_ctlr_1
= MT41J128MJT125_EMIF_READ_LATENCY_400MHz
|
247 #ifdef CONFIG_SPL_OS_BOOT
248 int spl_start_uboot(void)
250 #ifdef CONFIG_SPL_SERIAL_SUPPORT
251 /* break into full u-boot on 'c' */
252 if (serial_tstc() && serial_getc() == 'c')
256 #ifdef CONFIG_SPL_ENV_SUPPORT
259 if (env_get_yesno("boot_os") != 1)
267 const struct dpll_params
*get_dpll_ddr_params(void)
269 int ind
= get_sys_clk_index();
271 if (board_is_evm_sk())
272 return &dpll_ddr3_303MHz
[ind
];
273 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
274 return &dpll_ddr3_400MHz
[ind
];
275 else if (board_is_evm_15_or_later())
276 return &dpll_ddr3_303MHz
[ind
];
278 return &dpll_ddr2_266MHz
[ind
];
281 static u8
bone_not_connected_to_ac_power(void)
283 if (board_is_bone()) {
284 uchar pmic_status_reg
;
285 if (tps65217_reg_read(TPS65217_STATUS
,
288 if (!(pmic_status_reg
& TPS65217_PWR_SRC_AC_BITMASK
)) {
289 puts("No AC power, switching to default OPP\n");
296 const struct dpll_params
*get_dpll_mpu_params(void)
298 int ind
= get_sys_clk_index();
299 int freq
= am335x_get_efuse_mpu_max_freq(cdev
);
301 if (bone_not_connected_to_ac_power())
304 if (board_is_pb() || board_is_bone_lt())
305 freq
= MPUPLL_M_1000
;
309 return &dpll_mpu_opp
[ind
][5];
311 return &dpll_mpu_opp
[ind
][4];
313 return &dpll_mpu_opp
[ind
][3];
315 return &dpll_mpu_opp
[ind
][2];
317 return &dpll_mpu_opp100
;
319 return &dpll_mpu_opp
[ind
][0];
322 return &dpll_mpu_opp
[ind
][0];
325 static void scale_vcores_bone(int freq
)
327 int usb_cur_lim
, mpu_vdd
;
330 * Only perform PMIC configurations if board rev > A1
331 * on Beaglebone White
333 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
336 #ifndef CONFIG_DM_I2C
337 if (i2c_probe(TPS65217_CHIP_PM
))
340 if (power_tps65217_init(0))
346 * On Beaglebone White we need to ensure we have AC power
347 * before increasing the frequency.
349 if (bone_not_connected_to_ac_power())
353 * Override what we have detected since we know if we have
354 * a Beaglebone Black it supports 1GHz.
356 if (board_is_pb() || board_is_bone_lt())
357 freq
= MPUPLL_M_1000
;
361 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1325MV
;
362 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1800MA
;
365 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1275MV
;
366 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
369 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1200MV
;
370 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
376 mpu_vdd
= TPS65217_DCDC_VOLT_SEL_1100MV
;
377 usb_cur_lim
= TPS65217_USB_INPUT_CUR_LIMIT_1300MA
;
381 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE
,
384 TPS65217_USB_INPUT_CUR_LIMIT_MASK
))
385 puts("tps65217_reg_write failure\n");
387 /* Set DCDC3 (CORE) voltage to 1.10V */
388 if (tps65217_voltage_update(TPS65217_DEFDCDC3
,
389 TPS65217_DCDC_VOLT_SEL_1100MV
)) {
390 puts("tps65217_voltage_update failure\n");
394 /* Set DCDC2 (MPU) voltage */
395 if (tps65217_voltage_update(TPS65217_DEFDCDC2
, mpu_vdd
)) {
396 puts("tps65217_voltage_update failure\n");
401 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
402 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
404 if (board_is_bone()) {
405 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
407 TPS65217_LDO_VOLTAGE_OUT_3_3
,
409 puts("tps65217_reg_write failure\n");
411 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
413 TPS65217_LDO_VOLTAGE_OUT_1_8
,
415 puts("tps65217_reg_write failure\n");
418 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2
,
420 TPS65217_LDO_VOLTAGE_OUT_3_3
,
422 puts("tps65217_reg_write failure\n");
425 void scale_vcores_generic(int freq
)
427 int sil_rev
, mpu_vdd
;
430 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
431 * MPU frequencies we support we use a CORE voltage of
432 * 1.10V. For MPU voltage we need to switch based on
433 * the frequency we are running at.
435 #ifndef CONFIG_DM_I2C
436 if (i2c_probe(TPS65910_CTRL_I2C_ADDR
))
439 if (power_tps65910_init(0))
443 * Depending on MPU clock and PG we will need a different
444 * VDD to drive at that speed.
446 sil_rev
= readl(&cdev
->deviceid
) >> 28;
447 mpu_vdd
= am335x_get_tps65910_mpu_vdd(sil_rev
, freq
);
449 /* Tell the TPS65910 to use i2c */
450 tps65910_set_i2c_control();
452 /* First update MPU voltage. */
453 if (tps65910_voltage_update(MPU
, mpu_vdd
))
456 /* Second, update the CORE voltage. */
457 if (tps65910_voltage_update(CORE
, TPS65910_OP_REG_SEL_1_1_0
))
462 void gpi2c_init(void)
464 /* When needed to be invoked prior to BSS initialization */
465 static bool first_time
= true;
468 enable_i2c0_pin_mux();
469 #ifndef CONFIG_DM_I2C
470 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
,
471 CONFIG_SYS_OMAP24_I2C_SLAVE
);
477 void scale_vcores(void)
482 freq
= am335x_get_efuse_mpu_max_freq(cdev
);
484 if (board_is_beaglebonex())
485 scale_vcores_bone(freq
);
487 scale_vcores_generic(freq
);
490 void set_uart_mux_conf(void)
492 #if CONFIG_CONS_INDEX == 1
493 enable_uart0_pin_mux();
494 #elif CONFIG_CONS_INDEX == 2
495 enable_uart1_pin_mux();
496 #elif CONFIG_CONS_INDEX == 3
497 enable_uart2_pin_mux();
498 #elif CONFIG_CONS_INDEX == 4
499 enable_uart3_pin_mux();
500 #elif CONFIG_CONS_INDEX == 5
501 enable_uart4_pin_mux();
502 #elif CONFIG_CONS_INDEX == 6
503 enable_uart5_pin_mux();
507 void set_mux_conf_regs(void)
509 enable_board_pin_mux();
512 const struct ctrl_ioregs ioregs_evmsk
= {
513 .cm0ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
514 .cm1ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
515 .cm2ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
516 .dt0ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
517 .dt1ioctl
= MT41J128MJT125_IOCTRL_VALUE
,
520 const struct ctrl_ioregs ioregs_bonelt
= {
521 .cm0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
522 .cm1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
523 .cm2ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
524 .dt0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
525 .dt1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
528 const struct ctrl_ioregs ioregs_evm15
= {
529 .cm0ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
530 .cm1ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
531 .cm2ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
532 .dt0ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
533 .dt1ioctl
= MT41J512M8RH125_IOCTRL_VALUE
,
536 const struct ctrl_ioregs ioregs
= {
537 .cm0ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
538 .cm1ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
539 .cm2ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
540 .dt0ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
541 .dt1ioctl
= MT47H128M16RT25E_IOCTRL_VALUE
,
544 void sdram_init(void)
546 if (board_is_evm_sk()) {
548 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
549 * This is safe enough to do on older revs.
551 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
552 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
555 if (board_is_icev2()) {
556 gpio_request(ICE_GPIO_DDR_VTT_EN
, "ddr_vtt_en");
557 gpio_direction_output(ICE_GPIO_DDR_VTT_EN
, 1);
560 if (board_is_evm_sk())
561 config_ddr(303, &ioregs_evmsk
, &ddr3_data
,
562 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
563 else if (board_is_pb() || board_is_bone_lt())
564 config_ddr(400, &ioregs_bonelt
,
565 &ddr3_beagleblack_data
,
566 &ddr3_beagleblack_cmd_ctrl_data
,
567 &ddr3_beagleblack_emif_reg_data
, 0);
568 else if (board_is_evm_15_or_later())
569 config_ddr(303, &ioregs_evm15
, &ddr3_evm_data
,
570 &ddr3_evm_cmd_ctrl_data
, &ddr3_evm_emif_reg_data
, 0);
571 else if (board_is_icev2())
572 config_ddr(400, &ioregs_evmsk
, &ddr3_icev2_data
,
573 &ddr3_icev2_cmd_ctrl_data
, &ddr3_icev2_emif_reg_data
,
575 else if (board_is_gp_evm())
576 config_ddr(266, &ioregs
, &ddr2_data
,
577 &ddr2_cmd_ctrl_data
, &ddr2_evm_emif_reg_data
, 0);
579 config_ddr(266, &ioregs
, &ddr2_data
,
580 &ddr2_cmd_ctrl_data
, &ddr2_emif_reg_data
, 0);
584 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
585 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
586 static void request_and_set_gpio(int gpio
, char *name
, int val
)
590 ret
= gpio_request(gpio
, name
);
592 printf("%s: Unable to request %s\n", __func__
, name
);
596 ret
= gpio_direction_output(gpio
, 0);
598 printf("%s: Unable to set %s as output\n", __func__
, name
);
602 gpio_set_value(gpio
, val
);
610 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
611 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
614 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
615 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
616 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
617 * give 50MHz output for Eth0 and 1.
619 static struct clk_synth cdce913_data
= {
628 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
629 defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
631 #define MAX_CPSW_SLAVES 2
633 /* At the moment, we do not want to stop booting for any failures here */
634 int ft_board_setup(void *fdt
, bd_t
*bd
)
636 const char *slave_path
, *enet_name
;
637 int enetnode
, slavenode
, phynode
;
638 struct udevice
*ethdev
;
644 /* phy address fixup needed only on beagle bone family */
645 if (!board_is_beaglebonex())
648 for (i
= 0; i
< MAX_CPSW_SLAVES
; i
++) {
649 sprintf(alias
, "ethernet%d", i
);
651 slave_path
= fdt_get_alias(fdt
, alias
);
655 slavenode
= fdt_path_offset(fdt
, slave_path
);
659 enetnode
= fdt_parent_offset(fdt
, slavenode
);
660 enet_name
= fdt_get_name(fdt
, enetnode
, NULL
);
662 ethdev
= eth_get_dev_by_name(enet_name
);
666 phy_addr
= cpsw_get_slave_phy_addr(ethdev
, i
);
668 /* check for phy_id as well as phy-handle properties */
669 ret
= fdtdec_get_int_array_count(fdt
, slavenode
, "phy_id",
672 if (phy_id
[1] != phy_addr
) {
673 printf("fixing up phy_id for %s, old: %d, new: %d\n",
674 alias
, phy_id
[1], phy_addr
);
676 phy_id
[0] = cpu_to_fdt32(phy_id
[0]);
677 phy_id
[1] = cpu_to_fdt32(phy_addr
);
678 do_fixup_by_path(fdt
, slave_path
, "phy_id",
679 phy_id
, sizeof(phy_id
), 0);
682 phynode
= fdtdec_lookup_phandle(fdt
, slavenode
,
687 ret
= fdtdec_get_int(fdt
, phynode
, "reg", -ENOENT
);
691 if (ret
!= phy_addr
) {
692 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
693 alias
, ret
, phy_addr
);
695 fdt_setprop_u32(fdt
, phynode
, "reg",
696 cpu_to_fdt32(phy_addr
));
707 * Basic board specific setup. Pinmux has been handled already.
711 #if defined(CONFIG_HW_WATCHDOG)
715 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
716 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
720 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
721 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
722 if (board_is_icev2()) {
726 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL
);
727 /* Make J19 status available on GPIO1_26 */
728 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL
);
730 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL
);
732 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
733 * jumpers near the port. Read the jumper value and set
734 * the pinmux, external mux and PHY clock accordingly.
735 * As jumper line is overridden by PHY RX_DV pin immediately
736 * after bootstrap (power-up/reset), we need to sample
737 * it during PHY reset using GPIO rising edge detection.
739 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET
);
740 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
741 reg
= readl(GPIO0_RISINGDETECT
) | BIT(11);
742 writel(reg
, GPIO0_RISINGDETECT
);
743 reg
= readl(GPIO1_RISINGDETECT
) | BIT(26);
744 writel(reg
, GPIO1_RISINGDETECT
);
745 /* Reset PHYs to capture the Jumper setting */
746 gpio_set_value(GPIO_PHY_RESET
, 0);
747 udelay(2); /* PHY datasheet states 1uS min. */
748 gpio_set_value(GPIO_PHY_RESET
, 1);
750 reg
= readl(GPIO0_IRQSTATUSRAW
) & BIT(11);
752 writel(reg
, GPIO0_IRQSTATUS1
); /* clear irq */
754 printf("ETH0, CPSW\n");
757 printf("ETH0, PRU\n");
758 cdce913_data
.pdiv3
= 4; /* 25MHz PHY clk */
761 reg
= readl(GPIO1_IRQSTATUSRAW
) & BIT(26);
763 writel(reg
, GPIO1_IRQSTATUS1
); /* clear irq */
765 printf("ETH1, CPSW\n");
766 gpio_set_value(GPIO_MUX_MII_CTRL
, 1);
769 printf("ETH1, PRU\n");
770 cdce913_data
.pdiv2
= 4; /* 25MHz PHY clk */
773 /* disable rising edge IRQs */
774 reg
= readl(GPIO0_RISINGDETECT
) & ~BIT(11);
775 writel(reg
, GPIO0_RISINGDETECT
);
776 reg
= readl(GPIO1_RISINGDETECT
) & ~BIT(26);
777 writel(reg
, GPIO1_RISINGDETECT
);
779 rv
= setup_clock_synthesizer(&cdce913_data
);
781 printf("Clock synthesizer setup failed %d\n", rv
);
786 gpio_set_value(GPIO_PHY_RESET
, 0);
787 udelay(2); /* PHY datasheet states 1uS min. */
788 gpio_set_value(GPIO_PHY_RESET
, 1);
795 #ifdef CONFIG_BOARD_LATE_INIT
796 int board_late_init(void)
799 #if !defined(CONFIG_SPL_BUILD)
801 uint32_t mac_hi
, mac_lo
;
804 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
807 if (board_is_bone_lt()) {
808 /* BeagleBoard.org BeagleBone Black Wireless: */
809 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
812 /* SeeedStudio BeagleBone Green Wireless */
813 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
816 /* BeagleBoard.org BeagleBone Blue */
817 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
826 set_board_info_env(name
);
829 * Default FIT boot on HS devices. Non FIT images are not allowed
832 if (get_device_type() == HS_DEVICE
)
833 env_set("boot_fit", "1");
836 #if !defined(CONFIG_SPL_BUILD)
837 /* try reading mac address from efuse */
838 mac_lo
= readl(&cdev
->macid0l
);
839 mac_hi
= readl(&cdev
->macid0h
);
840 mac_addr
[0] = mac_hi
& 0xFF;
841 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
842 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
843 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
844 mac_addr
[4] = mac_lo
& 0xFF;
845 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
847 if (!env_get("ethaddr")) {
848 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
850 if (is_valid_ethaddr(mac_addr
))
851 eth_env_set_enetaddr("ethaddr", mac_addr
);
854 mac_lo
= readl(&cdev
->macid1l
);
855 mac_hi
= readl(&cdev
->macid1h
);
856 mac_addr
[0] = mac_hi
& 0xFF;
857 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
858 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
859 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
860 mac_addr
[4] = mac_lo
& 0xFF;
861 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
863 if (!env_get("eth1addr")) {
864 if (is_valid_ethaddr(mac_addr
))
865 eth_env_set_enetaddr("eth1addr", mac_addr
);
869 if (!env_get("serial#")) {
870 char *board_serial
= env_get("board_serial");
871 char *ethaddr
= env_get("ethaddr");
873 if (!board_serial
|| !strncmp(board_serial
, "unknown", 7))
874 env_set("serial#", ethaddr
);
876 env_set("serial#", board_serial
);
879 /* Just probe the potentially supported cdce913 device */
880 uclass_get_device(UCLASS_CLK
, 0, &dev
);
887 #if !CONFIG_IS_ENABLED(OF_CONTROL)
888 struct cpsw_slave_data slave_data
[] = {
890 .slave_reg_ofs
= CPSW_SLAVE0_OFFSET
,
891 .sliver_reg_ofs
= CPSW_SLIVER0_OFFSET
,
895 .slave_reg_ofs
= CPSW_SLAVE1_OFFSET
,
896 .sliver_reg_ofs
= CPSW_SLIVER1_OFFSET
,
901 struct cpsw_platform_data am335_eth_data
= {
902 .cpsw_base
= CPSW_BASE
,
903 .version
= CPSW_CTRL_VERSION_2
,
904 .bd_ram_ofs
= CPSW_BD_OFFSET
,
905 .ale_reg_ofs
= CPSW_ALE_OFFSET
,
906 .cpdma_reg_ofs
= CPSW_CPDMA_OFFSET
,
907 .mdio_div
= CPSW_MDIO_DIV
,
908 .host_port_reg_ofs
= CPSW_HOST_PORT_OFFSET
,
911 .slave_data
= slave_data
,
913 .bd_ram_ofs
= 0x2000,
916 .mdio_base
= 0x4a101000,
917 .gmii_sel
= 0x44e10650,
918 .phy_sel_compat
= "ti,am3352-cpsw-phy-sel",
919 .syscon_addr
= 0x44e10630,
920 .macid_sel_compat
= "cpsw,am33xx",
923 struct eth_pdata cpsw_pdata
= {
924 .iobase
= 0x4a100000,
926 .priv_pdata
= &am335_eth_data
,
929 U_BOOT_DEVICE(am335x_eth
) = {
931 .platdata
= &cpsw_pdata
,
935 #ifdef CONFIG_SPL_LOAD_FIT
936 int board_fit_config_name_match(const char *name
)
938 if (board_is_gp_evm() && !strcmp(name
, "am335x-evm"))
940 else if (board_is_bone() && !strcmp(name
, "am335x-bone"))
942 else if (board_is_bone_lt() && !strcmp(name
, "am335x-boneblack"))
944 else if (board_is_pb() && !strcmp(name
, "am335x-pocketbeagle"))
946 else if (board_is_evm_sk() && !strcmp(name
, "am335x-evmsk"))
948 else if (board_is_bbg1() && !strcmp(name
, "am335x-bonegreen"))
950 else if (board_is_icev2() && !strcmp(name
, "am335x-icev2"))
957 #ifdef CONFIG_TI_SECURE_DEVICE
958 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
960 secure_boot_verify_image(p_image
, p_size
);
964 #if !CONFIG_IS_ENABLED(OF_CONTROL)
965 static const struct omap_hsmmc_plat am335x_mmc0_platdata
= {
966 .base_addr
= (struct hsmmc
*)OMAP_HSMMC1_BASE
,
967 .cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
| MMC_MODE_4BIT
,
969 .cfg
.f_max
= 52000000,
970 .cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
,
971 .cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
,
974 U_BOOT_DEVICE(am335x_mmc0
) = {
975 .name
= "omap_hsmmc",
976 .platdata
= &am335x_mmc0_platdata
,
979 static const struct omap_hsmmc_plat am335x_mmc1_platdata
= {
980 .base_addr
= (struct hsmmc
*)OMAP_HSMMC2_BASE
,
981 .cfg
.host_caps
= MMC_MODE_HS_52MHz
| MMC_MODE_HS
| MMC_MODE_8BIT
,
983 .cfg
.f_max
= 52000000,
984 .cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
,
985 .cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
,
988 U_BOOT_DEVICE(am335x_mmc1
) = {
989 .name
= "omap_hsmmc",
990 .platdata
= &am335x_mmc1_platdata
,