board/ti/am335x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM335X based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <errno.h>
  14 #include <init.h>
  15 #include <malloc.h>
  16 #include <net.h>
  17 #include <spl.h>
  18 #include <serial.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/clk_synthesizer.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/mem.h>
  29 #include <asm/io.h>
  30 #include <asm/emif.h>
  31 #include <asm/gpio.h>
  32 #include <asm/omap_common.h>
  33 #include <asm/omap_sec_common.h>
  34 #include <asm/omap_mmc.h>
  35 #include <i2c.h>
  36 #include <miiphy.h>
  37 #include <cpsw.h>
  38 #include <power/tps65217.h>
  39 #include <power/tps65910.h>
  40 #include <env_internal.h>
  41 #include <watchdog.h>
  42 #include "../common/board_detect.h"
  43 #include "board.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 /* GPIO that controls power to DDR on EVM-SK */
  48 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  49 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  50 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  51 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  52 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  53 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  54 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  55 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  56 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  57
  58 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  59
  60 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  61 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  62
  63 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  64 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  65
  66 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  67 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  68
  69 /*
  70  * Read header information from EEPROM into global structure.
  71  */
  72 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  73 void do_board_detect(void)
  74 {
  75         enable_i2c0_pin_mux();
  76 #ifndef CONFIG_DM_I2C
  77         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  78 #endif
  79         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  80                                  CONFIG_EEPROM_CHIP_ADDRESS))
  81                 printf("ti_i2c_eeprom_init failed\n");
  82 }
  83 #endif
  84
  85 #ifndef CONFIG_DM_SERIAL
  86 struct serial_device *default_serial_console(void)
  87 {
  88         if (board_is_icev2())
  89                 return &eserial4_device;
  90         else
  91                 return &eserial1_device;
  92 }
  93 #endif
  94
  95 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  96 static const struct ddr_data ddr2_data = {
  97         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  98         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  99         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 100 };
 101
 102 static const struct cmd_control ddr2_cmd_ctrl_data = {
 103         .cmd0csratio = MT47H128M16RT25E_RATIO,
 104
 105         .cmd1csratio = MT47H128M16RT25E_RATIO,
 106
 107         .cmd2csratio = MT47H128M16RT25E_RATIO,
 108 };
 109
 110 static const struct emif_regs ddr2_emif_reg_data = {
 111         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 112         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 113         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 114         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 115         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 116         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 117 };
 118
 119 static const struct emif_regs ddr2_evm_emif_reg_data = {
 120         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 121         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 122         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 123         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 124         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 125         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 126         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 127 };
 128
 129 static const struct ddr_data ddr3_data = {
 130         .datardsratio0 = MT41J128MJT125_RD_DQS,
 131         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 132         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 133         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 134 };
 135
 136 static const struct ddr_data ddr3_beagleblack_data = {
 137         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 138         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 139         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 140         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 141 };
 142
 143 static const struct ddr_data ddr3_evm_data = {
 144         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 145         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 146         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 147         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 148 };
 149
 150 static const struct ddr_data ddr3_icev2_data = {
 151         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 152         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 153         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 154         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 155 };
 156
 157 static const struct cmd_control ddr3_cmd_ctrl_data = {
 158         .cmd0csratio = MT41J128MJT125_RATIO,
 159         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 160
 161         .cmd1csratio = MT41J128MJT125_RATIO,
 162         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 163
 164         .cmd2csratio = MT41J128MJT125_RATIO,
 165         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 166 };
 167
 168 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 169         .cmd0csratio = MT41K256M16HA125E_RATIO,
 170         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 171
 172         .cmd1csratio = MT41K256M16HA125E_RATIO,
 173         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 174
 175         .cmd2csratio = MT41K256M16HA125E_RATIO,
 176         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 177 };
 178
 179 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 180         .cmd0csratio = MT41J512M8RH125_RATIO,
 181         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 182
 183         .cmd1csratio = MT41J512M8RH125_RATIO,
 184         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 185
 186         .cmd2csratio = MT41J512M8RH125_RATIO,
 187         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 188 };
 189
 190 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 191         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 192         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 193
 194         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 195         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 196
 197         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 198         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 199 };
 200
 201 static struct emif_regs ddr3_emif_reg_data = {
 202         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 203         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 204         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 205         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 206         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 207         .zq_config = MT41J128MJT125_ZQ_CFG,
 208         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 209                                 PHY_EN_DYN_PWRDN,
 210 };
 211
 212 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 213         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 214         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 215         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 216         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 217         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 218         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 219         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 220         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 221 };
 222
 223 static struct emif_regs ddr3_evm_emif_reg_data = {
 224         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 225         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 226         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 227         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 228         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 229         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 230         .zq_config = MT41J512M8RH125_ZQ_CFG,
 231         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 232                                 PHY_EN_DYN_PWRDN,
 233 };
 234
 235 static struct emif_regs ddr3_icev2_emif_reg_data = {
 236         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 237         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 238         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 239         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 240         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 241         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 242         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 243                                 PHY_EN_DYN_PWRDN,
 244 };
 245
 246 #ifdef CONFIG_SPL_OS_BOOT
 247 int spl_start_uboot(void)
 248 {
 249 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 250         /* break into full u-boot on 'c' */
 251         if (serial_tstc() && serial_getc() == 'c')
 252                 return 1;
 253 #endif
 254
 255 #ifdef CONFIG_SPL_ENV_SUPPORT
 256         env_init();
 257         env_load();
 258         if (env_get_yesno("boot_os") != 1)
 259                 return 1;
 260 #endif
 261
 262         return 0;
 263 }
 264 #endif
 265
 266 const struct dpll_params *get_dpll_ddr_params(void)
 267 {
 268         int ind = get_sys_clk_index();
 269
 270         if (board_is_evm_sk())
 271                 return &dpll_ddr3_303MHz[ind];
 272         else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
 273                 return &dpll_ddr3_400MHz[ind];
 274         else if (board_is_evm_15_or_later())
 275                 return &dpll_ddr3_303MHz[ind];
 276         else
 277                 return &dpll_ddr2_266MHz[ind];
 278 }
 279
 280 static u8 bone_not_connected_to_ac_power(void)
 281 {
 282         if (board_is_bone()) {
 283                 uchar pmic_status_reg;
 284                 if (tps65217_reg_read(TPS65217_STATUS,
 285                                       &pmic_status_reg))
 286                         return 1;
 287                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 288                         puts("No AC power, switching to default OPP\n");
 289                         return 1;
 290                 }
 291         }
 292         return 0;
 293 }
 294
 295 const struct dpll_params *get_dpll_mpu_params(void)
 296 {
 297         int ind = get_sys_clk_index();
 298         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 299
 300         if (bone_not_connected_to_ac_power())
 301                 freq = MPUPLL_M_600;
 302
 303         if (board_is_pb() || board_is_bone_lt())
 304                 freq = MPUPLL_M_1000;
 305
 306         switch (freq) {
 307         case MPUPLL_M_1000:
 308                 return &dpll_mpu_opp[ind][5];
 309         case MPUPLL_M_800:
 310                 return &dpll_mpu_opp[ind][4];
 311         case MPUPLL_M_720:
 312                 return &dpll_mpu_opp[ind][3];
 313         case MPUPLL_M_600:
 314                 return &dpll_mpu_opp[ind][2];
 315         case MPUPLL_M_500:
 316                 return &dpll_mpu_opp100;
 317         case MPUPLL_M_300:
 318                 return &dpll_mpu_opp[ind][0];
 319         }
 320
 321         return &dpll_mpu_opp[ind][0];
 322 }
 323
 324 static void scale_vcores_bone(int freq)
 325 {
 326         int usb_cur_lim, mpu_vdd;
 327
 328         /*
 329          * Only perform PMIC configurations if board rev > A1
 330          * on Beaglebone White
 331          */
 332         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 333                 return;
 334
 335 #ifndef CONFIG_DM_I2C
 336         if (i2c_probe(TPS65217_CHIP_PM))
 337                 return;
 338 #else
 339         if (power_tps65217_init(0))
 340                 return;
 341 #endif
 342
 343
 344         /*
 345          * On Beaglebone White we need to ensure we have AC power
 346          * before increasing the frequency.
 347          */
 348         if (bone_not_connected_to_ac_power())
 349                 freq = MPUPLL_M_600;
 350
 351         /*
 352          * Override what we have detected since we know if we have
 353          * a Beaglebone Black it supports 1GHz.
 354          */
 355         if (board_is_pb() || board_is_bone_lt())
 356                 freq = MPUPLL_M_1000;
 357
 358         switch (freq) {
 359         case MPUPLL_M_1000:
 360                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 361                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 362                 break;
 363         case MPUPLL_M_800:
 364                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 365                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 366                 break;
 367         case MPUPLL_M_720:
 368                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 369                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 370                 break;
 371         case MPUPLL_M_600:
 372         case MPUPLL_M_500:
 373         case MPUPLL_M_300:
 374         default:
 375                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 376                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 377                 break;
 378         }
 379
 380         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 381                                TPS65217_POWER_PATH,
 382                                usb_cur_lim,
 383                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 384                 puts("tps65217_reg_write failure\n");
 385
 386         /* Set DCDC3 (CORE) voltage to 1.10V */
 387         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 388                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
 389                 puts("tps65217_voltage_update failure\n");
 390                 return;
 391         }
 392
 393         /* Set DCDC2 (MPU) voltage */
 394         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 395                 puts("tps65217_voltage_update failure\n");
 396                 return;
 397         }
 398
 399         /*
 400          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 401          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 402          */
 403         if (board_is_bone()) {
 404                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 405                                        TPS65217_DEFLS1,
 406                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 407                                        TPS65217_LDO_MASK))
 408                         puts("tps65217_reg_write failure\n");
 409         } else {
 410                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 411                                        TPS65217_DEFLS1,
 412                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
 413                                        TPS65217_LDO_MASK))
 414                         puts("tps65217_reg_write failure\n");
 415         }
 416
 417         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 418                                TPS65217_DEFLS2,
 419                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 420                                TPS65217_LDO_MASK))
 421                 puts("tps65217_reg_write failure\n");
 422 }
 423
 424 void scale_vcores_generic(int freq)
 425 {
 426         int sil_rev, mpu_vdd;
 427
 428         /*
 429          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 430          * MPU frequencies we support we use a CORE voltage of
 431          * 1.10V.  For MPU voltage we need to switch based on
 432          * the frequency we are running at.
 433          */
 434 #ifndef CONFIG_DM_I2C
 435         if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 436                 return;
 437 #else
 438         if (power_tps65910_init(0))
 439                 return;
 440 #endif
 441         /*
 442          * Depending on MPU clock and PG we will need a different
 443          * VDD to drive at that speed.
 444          */
 445         sil_rev = readl(&cdev->deviceid) >> 28;
 446         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 447
 448         /* Tell the TPS65910 to use i2c */
 449         tps65910_set_i2c_control();
 450
 451         /* First update MPU voltage. */
 452         if (tps65910_voltage_update(MPU, mpu_vdd))
 453                 return;
 454
 455         /* Second, update the CORE voltage. */
 456         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 457                 return;
 458
 459 }
 460
 461 void gpi2c_init(void)
 462 {
 463         /* When needed to be invoked prior to BSS initialization */
 464         static bool first_time = true;
 465
 466         if (first_time) {
 467                 enable_i2c0_pin_mux();
 468 #ifndef CONFIG_DM_I2C
 469                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 470                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 471 #endif
 472                 first_time = false;
 473         }
 474 }
 475
 476 void scale_vcores(void)
 477 {
 478         int freq;
 479
 480         gpi2c_init();
 481         freq = am335x_get_efuse_mpu_max_freq(cdev);
 482
 483         if (board_is_beaglebonex())
 484                 scale_vcores_bone(freq);
 485         else
 486                 scale_vcores_generic(freq);
 487 }
 488
 489 void set_uart_mux_conf(void)
 490 {
 491 #if CONFIG_CONS_INDEX == 1
 492         enable_uart0_pin_mux();
 493 #elif CONFIG_CONS_INDEX == 2
 494         enable_uart1_pin_mux();
 495 #elif CONFIG_CONS_INDEX == 3
 496         enable_uart2_pin_mux();
 497 #elif CONFIG_CONS_INDEX == 4
 498         enable_uart3_pin_mux();
 499 #elif CONFIG_CONS_INDEX == 5
 500         enable_uart4_pin_mux();
 501 #elif CONFIG_CONS_INDEX == 6
 502         enable_uart5_pin_mux();
 503 #endif
 504 }
 505
 506 void set_mux_conf_regs(void)
 507 {
 508         enable_board_pin_mux();
 509 }
 510
 511 const struct ctrl_ioregs ioregs_evmsk = {
 512         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 513         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 514         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 515         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 516         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 517 };
 518
 519 const struct ctrl_ioregs ioregs_bonelt = {
 520         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 521         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 522         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 523         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 524         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 525 };
 526
 527 const struct ctrl_ioregs ioregs_evm15 = {
 528         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 529         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 530         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 531         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 532         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 533 };
 534
 535 const struct ctrl_ioregs ioregs = {
 536         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 537         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 538         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 539         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 540         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 541 };
 542
 543 void sdram_init(void)
 544 {
 545         if (board_is_evm_sk()) {
 546                 /*
 547                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 548                  * This is safe enough to do on older revs.
 549                  */
 550                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 551                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 552         }
 553
 554         if (board_is_icev2()) {
 555                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 556                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 557         }
 558
 559         if (board_is_evm_sk())
 560                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 561                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 562         else if (board_is_pb() || board_is_bone_lt())
 563                 config_ddr(400, &ioregs_bonelt,
 564                            &ddr3_beagleblack_data,
 565                            &ddr3_beagleblack_cmd_ctrl_data,
 566                            &ddr3_beagleblack_emif_reg_data, 0);
 567         else if (board_is_evm_15_or_later())
 568                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 569                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 570         else if (board_is_icev2())
 571                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 572                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 573                            0);
 574         else if (board_is_gp_evm())
 575                 config_ddr(266, &ioregs, &ddr2_data,
 576                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 577         else
 578                 config_ddr(266, &ioregs, &ddr2_data,
 579                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 580 }
 581 #endif
 582
 583 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 584         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
 585 static void request_and_set_gpio(int gpio, char *name, int val)
 586 {
 587         int ret;
 588
 589         ret = gpio_request(gpio, name);
 590         if (ret < 0) {
 591                 printf("%s: Unable to request %s\n", __func__, name);
 592                 return;
 593         }
 594
 595         ret = gpio_direction_output(gpio, 0);
 596         if (ret < 0) {
 597                 printf("%s: Unable to set %s  as output\n", __func__, name);
 598                 goto err_free_gpio;
 599         }
 600
 601         gpio_set_value(gpio, val);
 602
 603         return;
 604
 605 err_free_gpio:
 606         gpio_free(gpio);
 607 }
 608
 609 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 610 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 611
 612 /**
 613  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 614  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 615  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 616  * give 50MHz output for Eth0 and 1.
 617  */
 618 static struct clk_synth cdce913_data = {
 619         .id = 0x81,
 620         .capacitor = 0x90,
 621         .mux = 0x6d,
 622         .pdiv2 = 0x2,
 623         .pdiv3 = 0x2,
 624 };
 625 #endif
 626
 627 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
 628         defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
 629
 630 #define MAX_CPSW_SLAVES 2
 631
 632 /* At the moment, we do not want to stop booting for any failures here */
 633 int ft_board_setup(void *fdt, bd_t *bd)
 634 {
 635         const char *slave_path, *enet_name;
 636         int enetnode, slavenode, phynode;
 637         struct udevice *ethdev;
 638         char alias[16];
 639         u32 phy_id[2];
 640         int phy_addr;
 641         int i, ret;
 642
 643         /* phy address fixup needed only on beagle bone family */
 644         if (!board_is_beaglebonex())
 645                 goto done;
 646
 647         for (i = 0; i < MAX_CPSW_SLAVES; i++) {
 648                 sprintf(alias, "ethernet%d", i);
 649
 650                 slave_path = fdt_get_alias(fdt, alias);
 651                 if (!slave_path)
 652                         continue;
 653
 654                 slavenode = fdt_path_offset(fdt, slave_path);
 655                 if (slavenode < 0)
 656                         continue;
 657
 658                 enetnode = fdt_parent_offset(fdt, slavenode);
 659                 enet_name = fdt_get_name(fdt, enetnode, NULL);
 660
 661                 ethdev = eth_get_dev_by_name(enet_name);
 662                 if (!ethdev)
 663                         continue;
 664
 665                 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
 666
 667                 /* check for phy_id as well as phy-handle properties */
 668                 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
 669                                                  phy_id, 2);
 670                 if (ret == 2) {
 671                         if (phy_id[1] != phy_addr) {
 672                                 printf("fixing up phy_id for %s, old: %d, new: %d\n",
 673                                        alias, phy_id[1], phy_addr);
 674
 675                                 phy_id[0] = cpu_to_fdt32(phy_id[0]);
 676                                 phy_id[1] = cpu_to_fdt32(phy_addr);
 677                                 do_fixup_by_path(fdt, slave_path, "phy_id",
 678                                                  phy_id, sizeof(phy_id), 0);
 679                         }
 680                 } else {
 681                         phynode = fdtdec_lookup_phandle(fdt, slavenode,
 682                                                         "phy-handle");
 683                         if (phynode < 0)
 684                                 continue;
 685
 686                         ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
 687                         if (ret < 0)
 688                                 continue;
 689
 690                         if (ret != phy_addr) {
 691                                 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
 692                                        alias, ret, phy_addr);
 693
 694                                 fdt_setprop_u32(fdt, phynode, "reg",
 695                                                 cpu_to_fdt32(phy_addr));
 696                         }
 697                 }
 698         }
 699
 700 done:
 701         return 0;
 702 }
 703 #endif
 704
 705 /*
 706  * Basic board specific setup.  Pinmux has been handled already.
 707  */
 708 int board_init(void)
 709 {
 710 #if defined(CONFIG_HW_WATCHDOG)
 711         hw_watchdog_init();
 712 #endif
 713
 714         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 715 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 716         gpmc_init();
 717 #endif
 718
 719 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 720         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
 721         if (board_is_icev2()) {
 722                 int rv;
 723                 u32 reg;
 724
 725                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 726                 /* Make J19 status available on GPIO1_26 */
 727                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 728
 729                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 730                 /*
 731                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 732                  * jumpers near the port. Read the jumper value and set
 733                  * the pinmux, external mux and PHY clock accordingly.
 734                  * As jumper line is overridden by PHY RX_DV pin immediately
 735                  * after bootstrap (power-up/reset), we need to sample
 736                  * it during PHY reset using GPIO rising edge detection.
 737                  */
 738                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 739                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 740                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 741                 writel(reg, GPIO0_RISINGDETECT);
 742                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 743                 writel(reg, GPIO1_RISINGDETECT);
 744                 /* Reset PHYs to capture the Jumper setting */
 745                 gpio_set_value(GPIO_PHY_RESET, 0);
 746                 udelay(2);      /* PHY datasheet states 1uS min. */
 747                 gpio_set_value(GPIO_PHY_RESET, 1);
 748
 749                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 750                 if (reg) {
 751                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 752                         /* RMII mode */
 753                         printf("ETH0, CPSW\n");
 754                 } else {
 755                         /* MII mode */
 756                         printf("ETH0, PRU\n");
 757                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 758                 }
 759
 760                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 761                 if (reg) {
 762                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 763                         /* RMII mode */
 764                         printf("ETH1, CPSW\n");
 765                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 766                 } else {
 767                         /* MII mode */
 768                         printf("ETH1, PRU\n");
 769                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 770                 }
 771
 772                 /* disable rising edge IRQs */
 773                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 774                 writel(reg, GPIO0_RISINGDETECT);
 775                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 776                 writel(reg, GPIO1_RISINGDETECT);
 777
 778                 rv = setup_clock_synthesizer(&cdce913_data);
 779                 if (rv) {
 780                         printf("Clock synthesizer setup failed %d\n", rv);
 781                         return rv;
 782                 }
 783
 784                 /* reset PHYs */
 785                 gpio_set_value(GPIO_PHY_RESET, 0);
 786                 udelay(2);      /* PHY datasheet states 1uS min. */
 787                 gpio_set_value(GPIO_PHY_RESET, 1);
 788         }
 789 #endif
 790
 791         return 0;
 792 }
 793
 794 #ifdef CONFIG_BOARD_LATE_INIT
 795 int board_late_init(void)
 796 {
 797         struct udevice *dev;
 798 #if !defined(CONFIG_SPL_BUILD)
 799         uint8_t mac_addr[6];
 800         uint32_t mac_hi, mac_lo;
 801 #endif
 802
 803 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 804         char *name = NULL;
 805
 806         if (board_is_bone_lt()) {
 807                 /* BeagleBoard.org BeagleBone Black Wireless: */
 808                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 809                         name = "BBBW";
 810                 }
 811                 /* SeeedStudio BeagleBone Green Wireless */
 812                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 813                         name = "BBGW";
 814                 }
 815                 /* BeagleBoard.org BeagleBone Blue */
 816                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 817                         name = "BBBL";
 818                 }
 819         }
 820
 821         if (board_is_bbg1())
 822                 name = "BBG1";
 823         if (board_is_bben())
 824                 name = "BBEN";
 825         set_board_info_env(name);
 826
 827         /*
 828          * Default FIT boot on HS devices. Non FIT images are not allowed
 829          * on HS devices.
 830          */
 831         if (get_device_type() == HS_DEVICE)
 832                 env_set("boot_fit", "1");
 833 #endif
 834
 835 #if !defined(CONFIG_SPL_BUILD)
 836         /* try reading mac address from efuse */
 837         mac_lo = readl(&cdev->macid0l);
 838         mac_hi = readl(&cdev->macid0h);
 839         mac_addr[0] = mac_hi & 0xFF;
 840         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 841         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 842         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 843         mac_addr[4] = mac_lo & 0xFF;
 844         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 845
 846         if (!env_get("ethaddr")) {
 847                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 848
 849                 if (is_valid_ethaddr(mac_addr))
 850                         eth_env_set_enetaddr("ethaddr", mac_addr);
 851         }
 852
 853         mac_lo = readl(&cdev->macid1l);
 854         mac_hi = readl(&cdev->macid1h);
 855         mac_addr[0] = mac_hi & 0xFF;
 856         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 857         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 858         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 859         mac_addr[4] = mac_lo & 0xFF;
 860         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 861
 862         if (!env_get("eth1addr")) {
 863                 if (is_valid_ethaddr(mac_addr))
 864                         eth_env_set_enetaddr("eth1addr", mac_addr);
 865         }
 866 #endif
 867
 868         if (!env_get("serial#")) {
 869                 char *board_serial = env_get("board_serial");
 870                 char *ethaddr = env_get("ethaddr");
 871
 872                 if (!board_serial || !strncmp(board_serial, "unknown", 7))
 873                         env_set("serial#", ethaddr);
 874                 else
 875                         env_set("serial#", board_serial);
 876         }
 877
 878         /* Just probe the potentially supported cdce913 device */
 879         uclass_get_device(UCLASS_CLK, 0, &dev);
 880
 881         return 0;
 882 }
 883 #endif
 884
 885 /* CPSW platdata */
 886 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 887 struct cpsw_slave_data slave_data[] = {
 888         {
 889                 .slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
 890                 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
 891                 .phy_addr       = 0,
 892         },
 893         {
 894                 .slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
 895                 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
 896                 .phy_addr       = 1,
 897         },
 898 };
 899
 900 struct cpsw_platform_data am335_eth_data = {
 901         .cpsw_base              = CPSW_BASE,
 902         .version                = CPSW_CTRL_VERSION_2,
 903         .bd_ram_ofs             = CPSW_BD_OFFSET,
 904         .ale_reg_ofs            = CPSW_ALE_OFFSET,
 905         .cpdma_reg_ofs          = CPSW_CPDMA_OFFSET,
 906         .mdio_div               = CPSW_MDIO_DIV,
 907         .host_port_reg_ofs      = CPSW_HOST_PORT_OFFSET,
 908         .channels               = 8,
 909         .slaves                 = 2,
 910         .slave_data             = slave_data,
 911         .ale_entries            = 1024,
 912         .bd_ram_ofs             = 0x2000,
 913         .mac_control            = 0x20,
 914         .active_slave           = 0,
 915         .mdio_base              = 0x4a101000,
 916         .gmii_sel               = 0x44e10650,
 917         .phy_sel_compat         = "ti,am3352-cpsw-phy-sel",
 918         .syscon_addr            = 0x44e10630,
 919         .macid_sel_compat       = "cpsw,am33xx",
 920 };
 921
 922 struct eth_pdata cpsw_pdata = {
 923         .iobase = 0x4a100000,
 924         .phy_interface = 0,
 925         .priv_pdata = &am335_eth_data,
 926 };
 927
 928 U_BOOT_DEVICE(am335x_eth) = {
 929         .name = "eth_cpsw",
 930         .platdata = &cpsw_pdata,
 931 };
 932 #endif
 933
 934 #ifdef CONFIG_SPL_LOAD_FIT
 935 int board_fit_config_name_match(const char *name)
 936 {
 937         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 938                 return 0;
 939         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 940                 return 0;
 941         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 942                 return 0;
 943         else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
 944                 return 0;
 945         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 946                 return 0;
 947         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 948                 return 0;
 949         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 950                 return 0;
 951         else
 952                 return -1;
 953 }
 954 #endif
 955
 956 #ifdef CONFIG_TI_SECURE_DEVICE
 957 void board_fit_image_post_process(void **p_image, size_t *p_size)
 958 {
 959         secure_boot_verify_image(p_image, p_size);
 960 }
 961 #endif
 962
 963 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 964 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
 965         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 966         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 967         .cfg.f_min = 400000,
 968         .cfg.f_max = 52000000,
 969         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 970         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 971 };
 972
 973 U_BOOT_DEVICE(am335x_mmc0) = {
 974         .name = "omap_hsmmc",
 975         .platdata = &am335x_mmc0_platdata,
 976 };
 977
 978 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
 979         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 980         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 981         .cfg.f_min = 400000,
 982         .cfg.f_max = 52000000,
 983         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 984         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 985 };
 986
 987 U_BOOT_DEVICE(am335x_mmc1) = {
 988         .name = "omap_hsmmc",
 989         .platdata = &am335x_mmc1_platdata,
 990 };
 991 #endif