board/ti/am335x/mux.c

   1 /*
   2  * mux.c
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <config.h>
  17 #include <asm/arch/common_def.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/io.h>
  20
  21 #define MUX_CFG(value, offset)  \
  22         __raw_writel(value, (CTRL_BASE + offset));
  23
  24 /* PAD Control Fields */
  25 #define SLEWCTRL        (0x1 << 6)
  26 #define RXACTIVE        (0x1 << 5)
  27 #define PULLUP_EN       (0x1 << 4) /* Pull UP Selection */
  28 #define PULLUDEN        (0x0 << 3) /* Pull up enabled */
  29 #define PULLUDDIS       (0x1 << 3) /* Pull up disabled */
  30 #define MODE(val)       val     /* used for Readability */
  31
  32 /*
  33  * PAD CONTROL OFFSETS
  34  * Field names corresponds to the pad signal name
  35  */
  36 struct pad_signals {
  37         int gpmc_ad0;
  38         int gpmc_ad1;
  39         int gpmc_ad2;
  40         int gpmc_ad3;
  41         int gpmc_ad4;
  42         int gpmc_ad5;
  43         int gpmc_ad6;
  44         int gpmc_ad7;
  45         int gpmc_ad8;
  46         int gpmc_ad9;
  47         int gpmc_ad10;
  48         int gpmc_ad11;
  49         int gpmc_ad12;
  50         int gpmc_ad13;
  51         int gpmc_ad14;
  52         int gpmc_ad15;
  53         int gpmc_a0;
  54         int gpmc_a1;
  55         int gpmc_a2;
  56         int gpmc_a3;
  57         int gpmc_a4;
  58         int gpmc_a5;
  59         int gpmc_a6;
  60         int gpmc_a7;
  61         int gpmc_a8;
  62         int gpmc_a9;
  63         int gpmc_a10;
  64         int gpmc_a11;
  65         int gpmc_wait0;
  66         int gpmc_wpn;
  67         int gpmc_be1n;
  68         int gpmc_csn0;
  69         int gpmc_csn1;
  70         int gpmc_csn2;
  71         int gpmc_csn3;
  72         int gpmc_clk;
  73         int gpmc_advn_ale;
  74         int gpmc_oen_ren;
  75         int gpmc_wen;
  76         int gpmc_be0n_cle;
  77         int lcd_data0;
  78         int lcd_data1;
  79         int lcd_data2;
  80         int lcd_data3;
  81         int lcd_data4;
  82         int lcd_data5;
  83         int lcd_data6;
  84         int lcd_data7;
  85         int lcd_data8;
  86         int lcd_data9;
  87         int lcd_data10;
  88         int lcd_data11;
  89         int lcd_data12;
  90         int lcd_data13;
  91         int lcd_data14;
  92         int lcd_data15;
  93         int lcd_vsync;
  94         int lcd_hsync;
  95         int lcd_pclk;
  96         int lcd_ac_bias_en;
  97         int mmc0_dat3;
  98         int mmc0_dat2;
  99         int mmc0_dat1;
 100         int mmc0_dat0;
 101         int mmc0_clk;
 102         int mmc0_cmd;
 103         int mii1_col;
 104         int mii1_crs;
 105         int mii1_rxerr;
 106         int mii1_txen;
 107         int mii1_rxdv;
 108         int mii1_txd3;
 109         int mii1_txd2;
 110         int mii1_txd1;
 111         int mii1_txd0;
 112         int mii1_txclk;
 113         int mii1_rxclk;
 114         int mii1_rxd3;
 115         int mii1_rxd2;
 116         int mii1_rxd1;
 117         int mii1_rxd0;
 118         int rmii1_refclk;
 119         int mdio_data;
 120         int mdio_clk;
 121         int spi0_sclk;
 122         int spi0_d0;
 123         int spi0_d1;
 124         int spi0_cs0;
 125         int spi0_cs1;
 126         int ecap0_in_pwm0_out;
 127         int uart0_ctsn;
 128         int uart0_rtsn;
 129         int uart0_rxd;
 130         int uart0_txd;
 131         int uart1_ctsn;
 132         int uart1_rtsn;
 133         int uart1_rxd;
 134         int uart1_txd;
 135         int i2c0_sda;
 136         int i2c0_scl;
 137         int mcasp0_aclkx;
 138         int mcasp0_fsx;
 139         int mcasp0_axr0;
 140         int mcasp0_ahclkr;
 141         int mcasp0_aclkr;
 142         int mcasp0_fsr;
 143         int mcasp0_axr1;
 144         int mcasp0_ahclkx;
 145         int xdma_event_intr0;
 146         int xdma_event_intr1;
 147         int nresetin_out;
 148         int porz;
 149         int nnmi;
 150         int osc0_in;
 151         int osc0_out;
 152         int rsvd1;
 153         int tms;
 154         int tdi;
 155         int tdo;
 156         int tck;
 157         int ntrst;
 158         int emu0;
 159         int emu1;
 160         int osc1_in;
 161         int osc1_out;
 162         int pmic_power_en;
 163         int rtc_porz;
 164         int rsvd2;
 165         int ext_wakeup;
 166         int enz_kaldo_1p8v;
 167         int usb0_dm;
 168         int usb0_dp;
 169         int usb0_ce;
 170         int usb0_id;
 171         int usb0_vbus;
 172         int usb0_drvvbus;
 173         int usb1_dm;
 174         int usb1_dp;
 175         int usb1_ce;
 176         int usb1_id;
 177         int usb1_vbus;
 178         int usb1_drvvbus;
 179         int ddr_resetn;
 180         int ddr_csn0;
 181         int ddr_cke;
 182         int ddr_ck;
 183         int ddr_nck;
 184         int ddr_casn;
 185         int ddr_rasn;
 186         int ddr_wen;
 187         int ddr_ba0;
 188         int ddr_ba1;
 189         int ddr_ba2;
 190         int ddr_a0;
 191         int ddr_a1;
 192         int ddr_a2;
 193         int ddr_a3;
 194         int ddr_a4;
 195         int ddr_a5;
 196         int ddr_a6;
 197         int ddr_a7;
 198         int ddr_a8;
 199         int ddr_a9;
 200         int ddr_a10;
 201         int ddr_a11;
 202         int ddr_a12;
 203         int ddr_a13;
 204         int ddr_a14;
 205         int ddr_a15;
 206         int ddr_odt;
 207         int ddr_d0;
 208         int ddr_d1;
 209         int ddr_d2;
 210         int ddr_d3;
 211         int ddr_d4;
 212         int ddr_d5;
 213         int ddr_d6;
 214         int ddr_d7;
 215         int ddr_d8;
 216         int ddr_d9;
 217         int ddr_d10;
 218         int ddr_d11;
 219         int ddr_d12;
 220         int ddr_d13;
 221         int ddr_d14;
 222         int ddr_d15;
 223         int ddr_dqm0;
 224         int ddr_dqm1;
 225         int ddr_dqs0;
 226         int ddr_dqsn0;
 227         int ddr_dqs1;
 228         int ddr_dqsn1;
 229         int ddr_vref;
 230         int ddr_vtp;
 231         int ddr_strben0;
 232         int ddr_strben1;
 233         int ain7;
 234         int ain6;
 235         int ain5;
 236         int ain4;
 237         int ain3;
 238         int ain2;
 239         int ain1;
 240         int ain0;
 241         int vrefp;
 242         int vrefn;
 243 };
 244
 245 struct module_pin_mux {
 246         short reg_offset;
 247         unsigned char val;
 248 };
 249
 250 /* Pad control register offset */
 251 #define PAD_CTRL_BASE   0x800
 252 #define OFFSET(x)       (unsigned int) (&((struct pad_signals *) \
 253                                 (PAD_CTRL_BASE))->x)
 254
 255 static struct module_pin_mux uart0_pin_mux[] = {
 256         {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART0_RXD */
 257         {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},              /* UART0_TXD */
 258         {-1},
 259 };
 260
 261 #ifdef CONFIG_MMC
 262 static struct module_pin_mux mmc0_pin_mux[] = {
 263         {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT3 */
 264         {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT2 */
 265         {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT1 */
 266         {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT0 */
 267         {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CLK */
 268         {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CMD */
 269         {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},           /* MMC0_WP */
 270         {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},   /* MMC0_CD */
 271         {-1},
 272 };
 273 #endif
 274
 275 /*
 276  * Configure the pin mux for the module
 277  */
 278 static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
 279 {
 280         int i;
 281
 282         if (!mod_pin_mux)
 283                 return;
 284
 285         for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
 286                 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
 287 }
 288
 289 void enable_uart0_pin_mux(void)
 290 {
 291         configure_module_pin_mux(uart0_pin_mux);
 292 }
 293
 294 #ifdef CONFIG_MMC
 295 void enable_mmc0_pin_mux(void)
 296 {
 297         configure_module_pin_mux(mmc0_pin_mux);
 298 }
 299 #endif