board/ti/am335x/mux.c

   1 /*
   2  * mux.c
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <common.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/mux.h>
  20 #include <asm/io.h>
  21 #include <i2c.h>
  22 #include "board.h"
  23
  24 static struct module_pin_mux uart0_pin_mux[] = {
  25         {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART0_RXD */
  26         {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},              /* UART0_TXD */
  27         {-1},
  28 };
  29
  30 static struct module_pin_mux uart1_pin_mux[] = {
  31         {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART1_RXD */
  32         {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},              /* UART1_TXD */
  33         {-1},
  34 };
  35
  36 static struct module_pin_mux uart2_pin_mux[] = {
  37         {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},  /* UART2_RXD */
  38         {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},                /* UART2_TXD */
  39         {-1},
  40 };
  41
  42 static struct module_pin_mux uart3_pin_mux[] = {
  43         {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},   /* UART3_RXD */
  44         {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},      /* UART3_TXD */
  45         {-1},
  46 };
  47
  48 static struct module_pin_mux uart4_pin_mux[] = {
  49         {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
  50         {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},               /* UART4_TXD */
  51         {-1},
  52 };
  53
  54 static struct module_pin_mux uart5_pin_mux[] = {
  55         {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},  /* UART5_RXD */
  56         {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},              /* UART5_TXD */
  57         {-1},
  58 };
  59
  60 static struct module_pin_mux mmc0_pin_mux[] = {
  61         {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT3 */
  62         {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT2 */
  63         {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT1 */
  64         {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT0 */
  65         {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CLK */
  66         {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CMD */
  67         {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},           /* MMC0_WP */
  68         {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},   /* MMC0_CD */
  69         {-1},
  70 };
  71
  72 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
  73         {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT3 */
  74         {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT2 */
  75         {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT1 */
  76         {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT0 */
  77         {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CLK */
  78         {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CMD */
  79         {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},   /* MMC0_CD */
  80         {-1},
  81 };
  82
  83 static struct module_pin_mux mmc1_pin_mux[] = {
  84         {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT3 */
  85         {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT2 */
  86         {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT1 */
  87         {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},   /* MMC1_DAT0 */
  88         {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},  /* MMC1_CLK */
  89         {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},  /* MMC1_CMD */
  90         {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},  /* MMC1_WP */
  91         {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},      /* MMC1_CD */
  92         {-1},
  93 };
  94
  95 static struct module_pin_mux i2c0_pin_mux[] = {
  96         {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  97                         PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  98         {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  99                         PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
 100         {-1},
 101 };
 102
 103 static struct module_pin_mux i2c1_pin_mux[] = {
 104         {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
 105                         PULLUDEN | SLEWCTRL)},  /* I2C_DATA */
 106         {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
 107                         PULLUDEN | SLEWCTRL)},  /* I2C_SCLK */
 108         {-1},
 109 };
 110
 111 static struct module_pin_mux spi0_pin_mux[] = {
 112         {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},   /* SPI0_SCLK */
 113         {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
 114                         PULLUDEN | PULLUP_EN)},                 /* SPI0_D0 */
 115         {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},     /* SPI0_D1 */
 116         {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
 117                         PULLUDEN | PULLUP_EN)},                 /* SPI0_CS0 */
 118         {-1},
 119 };
 120
 121 static struct module_pin_mux gpio0_7_pin_mux[] = {
 122         {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)},      /* GPIO0_7 */
 123         {-1},
 124 };
 125
 126 static struct module_pin_mux rgmii1_pin_mux[] = {
 127         {OFFSET(mii1_txen), MODE(2)},                   /* RGMII1_TCTL */
 128         {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},        /* RGMII1_RCTL */
 129         {OFFSET(mii1_txd3), MODE(2)},                   /* RGMII1_TD3 */
 130         {OFFSET(mii1_txd2), MODE(2)},                   /* RGMII1_TD2 */
 131         {OFFSET(mii1_txd1), MODE(2)},                   /* RGMII1_TD1 */
 132         {OFFSET(mii1_txd0), MODE(2)},                   /* RGMII1_TD0 */
 133         {OFFSET(mii1_txclk), MODE(2)},                  /* RGMII1_TCLK */
 134         {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},       /* RGMII1_RCLK */
 135         {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},        /* RGMII1_RD3 */
 136         {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},        /* RGMII1_RD2 */
 137         {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},        /* RGMII1_RD1 */
 138         {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},        /* RGMII1_RD0 */
 139         {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
 140         {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
 141         {-1},
 142 };
 143
 144 static struct module_pin_mux mii1_pin_mux[] = {
 145         {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},       /* MII1_RXERR */
 146         {OFFSET(mii1_txen), MODE(0)},                   /* MII1_TXEN */
 147         {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},        /* MII1_RXDV */
 148         {OFFSET(mii1_txd3), MODE(0)},                   /* MII1_TXD3 */
 149         {OFFSET(mii1_txd2), MODE(0)},                   /* MII1_TXD2 */
 150         {OFFSET(mii1_txd1), MODE(0)},                   /* MII1_TXD1 */
 151         {OFFSET(mii1_txd0), MODE(0)},                   /* MII1_TXD0 */
 152         {OFFSET(mii1_txclk), MODE(0) | RXACTIVE},       /* MII1_TXCLK */
 153         {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},       /* MII1_RXCLK */
 154         {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},        /* MII1_RXD3 */
 155         {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},        /* MII1_RXD2 */
 156         {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},        /* MII1_RXD1 */
 157         {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},        /* MII1_RXD0 */
 158         {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
 159         {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
 160         {-1},
 161 };
 162
 163 void enable_uart0_pin_mux(void)
 164 {
 165         configure_module_pin_mux(uart0_pin_mux);
 166 }
 167
 168 void enable_uart1_pin_mux(void)
 169 {
 170         configure_module_pin_mux(uart1_pin_mux);
 171 }
 172
 173 void enable_uart2_pin_mux(void)
 174 {
 175         configure_module_pin_mux(uart2_pin_mux);
 176 }
 177
 178 void enable_uart3_pin_mux(void)
 179 {
 180         configure_module_pin_mux(uart3_pin_mux);
 181 }
 182
 183 void enable_uart4_pin_mux(void)
 184 {
 185         configure_module_pin_mux(uart4_pin_mux);
 186 }
 187
 188 void enable_uart5_pin_mux(void)
 189 {
 190         configure_module_pin_mux(uart5_pin_mux);
 191 }
 192
 193 void enable_i2c0_pin_mux(void)
 194 {
 195         configure_module_pin_mux(i2c0_pin_mux);
 196 }
 197
 198 /*
 199  * The AM335x GP EVM, if daughter card(s) are connected, can have 8
 200  * different profiles.  These profiles determine what peripherals are
 201  * valid and need pinmux to be configured.
 202  */
 203 #define PROFILE_NONE    0x0
 204 #define PROFILE_0       (1 << 0)
 205 #define PROFILE_1       (1 << 1)
 206 #define PROFILE_2       (1 << 2)
 207 #define PROFILE_3       (1 << 3)
 208 #define PROFILE_4       (1 << 4)
 209 #define PROFILE_5       (1 << 5)
 210 #define PROFILE_6       (1 << 6)
 211 #define PROFILE_7       (1 << 7)
 212 #define PROFILE_MASK    0x7
 213 #define PROFILE_ALL     0xFF
 214
 215 /* CPLD registers */
 216 #define I2C_CPLD_ADDR   0x35
 217 #define CFG_REG         0x10
 218
 219 static unsigned short detect_daughter_board_profile(void)
 220 {
 221         unsigned short val;
 222
 223         if (i2c_probe(I2C_CPLD_ADDR))
 224                 return PROFILE_NONE;
 225
 226         if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
 227                 return PROFILE_NONE;
 228
 229         return (1 << (val & PROFILE_MASK));
 230 }
 231
 232 void enable_board_pin_mux(struct am335x_baseboard_id *header)
 233 {
 234         /* Do board-specific muxes. */
 235         if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) {
 236                 /* Beaglebone pinmux */
 237                 configure_module_pin_mux(i2c1_pin_mux);
 238                 configure_module_pin_mux(mii1_pin_mux);
 239                 configure_module_pin_mux(mmc0_pin_mux);
 240                 configure_module_pin_mux(mmc1_pin_mux);
 241         } else if (!strncmp(header->config, "SKU#01", 6)) {
 242                 /* General Purpose EVM */
 243                 unsigned short profile = detect_daughter_board_profile();
 244                 configure_module_pin_mux(rgmii1_pin_mux);
 245                 configure_module_pin_mux(mmc0_pin_mux);
 246                 /* In profile #2 i2c1 and spi0 conflict. */
 247                 if (profile & ~PROFILE_2)
 248                         configure_module_pin_mux(i2c1_pin_mux);
 249                 else if (profile == PROFILE_2) {
 250                         configure_module_pin_mux(mmc1_pin_mux);
 251                         configure_module_pin_mux(spi0_pin_mux);
 252                 }
 253         } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
 254                 /* Starter Kit EVM */
 255                 configure_module_pin_mux(i2c1_pin_mux);
 256                 configure_module_pin_mux(gpio0_7_pin_mux);
 257                 configure_module_pin_mux(rgmii1_pin_mux);
 258                 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
 259         } else {
 260                 puts("Unknown board, cannot configure pinmux.");
 261                 hang();
 262         }
 263 }