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common: Drop net.h from common header
[thirdparty/u-boot.git] / board / ti / am57xx / board.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 *
5 * Author: Felipe Balbi <balbi@ti.com>
6 *
7 * Based on board/ti/dra7xx/evm.c
8 */
9
10 #include <common.h>
11 #include <env.h>
12 #include <fdt_support.h>
13 #include <init.h>
14 #include <malloc.h>
15 #include <net.h>
16 #include <palmas.h>
17 #include <sata.h>
18 #include <serial.h>
19 #include <usb.h>
20 #include <errno.h>
21 #include <asm/omap_common.h>
22 #include <asm/omap_sec_common.h>
23 #include <asm/emif.h>
24 #include <asm/gpio.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/dra7xx_iodelay.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/sata.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/omap.h>
33 #include <usb.h>
34 #include <linux/usb/gadget.h>
35 #include <dwc3-uboot.h>
36 #include <dwc3-omap-uboot.h>
37 #include <ti-usb-phy-uboot.h>
38 #include <mmc.h>
39 #include <dm/uclass.h>
40 #include <hang.h>
41
42 #include "../common/board_detect.h"
43 #include "mux_data.h"
44
45 #ifdef CONFIG_SUPPORT_EMMC_BOOT
46 static int board_bootmode_has_emmc(void);
47 #endif
48
49 #define board_is_x15() board_ti_is("BBRDX15_")
50 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
51 !strncmp("B.10", board_ti_get_rev(), 3))
52 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
53 !strncmp("C.00", board_ti_get_rev(), 3))
54 #define board_is_am572x_evm() board_ti_is("AM572PM_")
55 #define board_is_am572x_evm_reva3() \
56 (board_ti_is("AM572PM_") && \
57 !strncmp("A.30", board_ti_get_rev(), 3))
58 #define board_is_am574x_idk() board_ti_is("AM574IDK")
59 #define board_is_am572x_idk() board_ti_is("AM572IDK")
60 #define board_is_am571x_idk() board_ti_is("AM571IDK")
61 #define board_is_bbai() board_ti_is("BBONE-AI")
62
63 #ifdef CONFIG_DRIVER_TI_CPSW
64 #include <cpsw.h>
65 #endif
66
67 DECLARE_GLOBAL_DATA_PTR;
68
69 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
70 /* GPIO 7_11 */
71 #define GPIO_DDR_VTT_EN 203
72
73 /* Touch screen controller to identify the LCD */
74 #define OSD_TS_FT_BUS_ADDRESS 0
75 #define OSD_TS_FT_CHIP_ADDRESS 0x38
76 #define OSD_TS_FT_REG_ID 0xA3
77 /*
78 * Touchscreen IDs for various OSD panels
79 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
80 */
81 /* Used on newer osd101t2587 Panels */
82 #define OSD_TS_FT_ID_5x46 0x54
83 /* Used on older osd101t2045 Panels */
84 #define OSD_TS_FT_ID_5606 0x08
85
86 #define SYSINFO_BOARD_NAME_MAX_LEN 45
87
88 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
89 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
90
91 const struct omap_sysinfo sysinfo = {
92 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
93 };
94
95 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
96 .dmm_lisa_map_3 = 0x80740300,
97 .is_ma_present = 0x1
98 };
99
100 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
101 .dmm_lisa_map_3 = 0x80640100,
102 .is_ma_present = 0x1
103 };
104
105 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
106 .dmm_lisa_map_2 = 0xc0600200,
107 .dmm_lisa_map_3 = 0x80600100,
108 .is_ma_present = 0x1
109 };
110
111 static const struct dmm_lisa_map_regs bbai_lisa_regs = {
112 .dmm_lisa_map_3 = 0x80640100,
113 .is_ma_present = 0x1
114 };
115
116 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
117 {
118 if (board_is_am571x_idk())
119 *dmm_lisa_regs = &am571x_idk_lisa_regs;
120 else if (board_is_am574x_idk())
121 *dmm_lisa_regs = &am574x_idk_lisa_regs;
122 else if (board_is_bbai())
123 *dmm_lisa_regs = &bbai_lisa_regs;
124 else
125 *dmm_lisa_regs = &beagle_x15_lisa_regs;
126 }
127
128 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
129 .sdram_config_init = 0x61851b32,
130 .sdram_config = 0x61851b32,
131 .sdram_config2 = 0x08000000,
132 .ref_ctrl = 0x000040F1,
133 .ref_ctrl_final = 0x00001035,
134 .sdram_tim1 = 0xcccf36ab,
135 .sdram_tim2 = 0x308f7fda,
136 .sdram_tim3 = 0x409f88a8,
137 .read_idle_ctrl = 0x00050000,
138 .zq_config = 0x5007190b,
139 .temp_alert_config = 0x00000000,
140 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
141 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
142 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
143 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
144 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
145 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
146 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
147 .emif_rd_wr_lvl_rmp_win = 0x00000000,
148 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
149 .emif_rd_wr_lvl_ctl = 0x00000000,
150 .emif_rd_wr_exec_thresh = 0x00000305
151 };
152
153 /* Ext phy ctrl regs 1-35 */
154 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
155 0x10040100,
156 0x00910091,
157 0x00950095,
158 0x009B009B,
159 0x009E009E,
160 0x00980098,
161 0x00340034,
162 0x00350035,
163 0x00340034,
164 0x00310031,
165 0x00340034,
166 0x007F007F,
167 0x007F007F,
168 0x007F007F,
169 0x007F007F,
170 0x007F007F,
171 0x00480048,
172 0x004A004A,
173 0x00520052,
174 0x00550055,
175 0x00500050,
176 0x00000000,
177 0x00600020,
178 0x40011080,
179 0x08102040,
180 0x0,
181 0x0,
182 0x0,
183 0x0,
184 0x0,
185 0x0,
186 0x0,
187 0x0,
188 0x0,
189 0x0
190 };
191
192 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
193 .sdram_config_init = 0x61851b32,
194 .sdram_config = 0x61851b32,
195 .sdram_config2 = 0x08000000,
196 .ref_ctrl = 0x000040F1,
197 .ref_ctrl_final = 0x00001035,
198 .sdram_tim1 = 0xcccf36b3,
199 .sdram_tim2 = 0x308f7fda,
200 .sdram_tim3 = 0x407f88a8,
201 .read_idle_ctrl = 0x00050000,
202 .zq_config = 0x5007190b,
203 .temp_alert_config = 0x00000000,
204 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
205 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
206 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
207 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
208 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
209 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
210 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
211 .emif_rd_wr_lvl_rmp_win = 0x00000000,
212 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
213 .emif_rd_wr_lvl_ctl = 0x00000000,
214 .emif_rd_wr_exec_thresh = 0x00000305
215 };
216
217 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
218 0x10040100,
219 0x00910091,
220 0x00950095,
221 0x009B009B,
222 0x009E009E,
223 0x00980098,
224 0x00340034,
225 0x00350035,
226 0x00340034,
227 0x00310031,
228 0x00340034,
229 0x007F007F,
230 0x007F007F,
231 0x007F007F,
232 0x007F007F,
233 0x007F007F,
234 0x00480048,
235 0x004A004A,
236 0x00520052,
237 0x00550055,
238 0x00500050,
239 0x00000000,
240 0x00600020,
241 0x40011080,
242 0x08102040,
243 0x0,
244 0x0,
245 0x0,
246 0x0,
247 0x0,
248 0x0,
249 0x0,
250 0x0,
251 0x0,
252 0x0
253 };
254
255 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
256 .sdram_config_init = 0x61863332,
257 .sdram_config = 0x61863332,
258 .sdram_config2 = 0x08000000,
259 .ref_ctrl = 0x0000514d,
260 .ref_ctrl_final = 0x0000144a,
261 .sdram_tim1 = 0xd333887c,
262 .sdram_tim2 = 0x30b37fe3,
263 .sdram_tim3 = 0x409f8ad8,
264 .read_idle_ctrl = 0x00050000,
265 .zq_config = 0x5007190b,
266 .temp_alert_config = 0x00000000,
267 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
268 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
269 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
270 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
271 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
272 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
273 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
274 .emif_rd_wr_lvl_rmp_win = 0x00000000,
275 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
276 .emif_rd_wr_lvl_ctl = 0x00000000,
277 .emif_rd_wr_exec_thresh = 0x00000305
278 };
279
280 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
281 .sdram_config_init = 0x61863332,
282 .sdram_config = 0x61863332,
283 .sdram_config2 = 0x08000000,
284 .ref_ctrl = 0x0000514d,
285 .ref_ctrl_final = 0x0000144a,
286 .sdram_tim1 = 0xd333887c,
287 .sdram_tim2 = 0x30b37fe3,
288 .sdram_tim3 = 0x409f8ad8,
289 .read_idle_ctrl = 0x00050000,
290 .zq_config = 0x5007190b,
291 .temp_alert_config = 0x00000000,
292 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
293 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
294 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
295 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
296 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
297 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
298 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
299 .emif_rd_wr_lvl_rmp_win = 0x00000000,
300 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
301 .emif_rd_wr_lvl_ctl = 0x00000000,
302 .emif_rd_wr_exec_thresh = 0x00000305,
303 .emif_ecc_ctrl_reg = 0xD0000001,
304 .emif_ecc_address_range_1 = 0x3FFF0000,
305 .emif_ecc_address_range_2 = 0x00000000
306 };
307
308 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
309 {
310 switch (emif_nr) {
311 case 1:
312 if (board_is_am571x_idk())
313 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
314 else if (board_is_am574x_idk())
315 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
316 else
317 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
318 break;
319 case 2:
320 if (board_is_am574x_idk())
321 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
322 else
323 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
324 break;
325 }
326 }
327
328 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
329 {
330 switch (emif_nr) {
331 case 1:
332 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
333 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
334 break;
335 case 2:
336 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
337 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
338 break;
339 }
340 }
341
342 struct vcores_data beagle_x15_volts = {
343 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
344 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
345 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
346 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
347 .mpu.pmic = &tps659038,
348 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
349
350 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
351 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
352 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
353 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
354 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
355 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
356 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
357 .eve.addr = TPS659038_REG_ADDR_SMPS45,
358 .eve.pmic = &tps659038,
359 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
360
361 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
362 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
363 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
364 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
365 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
366 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
367 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
368 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
369 .gpu.pmic = &tps659038,
370 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
371
372 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
373 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
374 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
375 .core.addr = TPS659038_REG_ADDR_SMPS6,
376 .core.pmic = &tps659038,
377
378 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
379 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
380 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
381 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
382 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
383 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
384 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385 .iva.addr = TPS659038_REG_ADDR_SMPS45,
386 .iva.pmic = &tps659038,
387 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
388 };
389
390 struct vcores_data am572x_idk_volts = {
391 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
392 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
393 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
394 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
395 .mpu.pmic = &tps659038,
396 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
397
398 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
399 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
400 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
401 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
402 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
403 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
404 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
405 .eve.addr = TPS659038_REG_ADDR_SMPS45,
406 .eve.pmic = &tps659038,
407 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
408
409 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
410 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
411 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
412 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
413 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
414 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
415 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
416 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
417 .gpu.pmic = &tps659038,
418 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
419
420 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
421 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
422 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
423 .core.addr = TPS659038_REG_ADDR_SMPS7,
424 .core.pmic = &tps659038,
425
426 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
427 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
428 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
429 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
430 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
431 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
432 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433 .iva.addr = TPS659038_REG_ADDR_SMPS8,
434 .iva.pmic = &tps659038,
435 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
436 };
437
438 struct vcores_data am571x_idk_volts = {
439 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
440 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
441 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
442 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
443 .mpu.pmic = &tps659038,
444 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
445
446 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
447 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
448 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
449 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
450 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
451 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
452 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
453 .eve.addr = TPS659038_REG_ADDR_SMPS45,
454 .eve.pmic = &tps659038,
455 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
456
457 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
458 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
459 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
460 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
461 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
462 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
463 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
464 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
465 .gpu.pmic = &tps659038,
466 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
467
468 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
469 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
470 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
471 .core.addr = TPS659038_REG_ADDR_SMPS7,
472 .core.pmic = &tps659038,
473
474 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
475 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
476 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
477 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
478 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
479 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
480 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
481 .iva.addr = TPS659038_REG_ADDR_SMPS45,
482 .iva.pmic = &tps659038,
483 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
484 };
485
486 int get_voltrail_opp(int rail_offset)
487 {
488 int opp;
489
490 switch (rail_offset) {
491 case VOLT_MPU:
492 opp = DRA7_MPU_OPP;
493 break;
494 case VOLT_CORE:
495 opp = DRA7_CORE_OPP;
496 break;
497 case VOLT_GPU:
498 opp = DRA7_GPU_OPP;
499 break;
500 case VOLT_EVE:
501 opp = DRA7_DSPEVE_OPP;
502 break;
503 case VOLT_IVA:
504 opp = DRA7_IVA_OPP;
505 break;
506 default:
507 opp = OPP_NOM;
508 }
509
510 return opp;
511 }
512
513
514 #ifdef CONFIG_SPL_BUILD
515 /* No env to setup for SPL */
516 static inline void setup_board_eeprom_env(void) { }
517
518 /* Override function to read eeprom information */
519 void do_board_detect(void)
520 {
521 int rc;
522
523 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
524 CONFIG_EEPROM_CHIP_ADDRESS);
525 if (rc)
526 printf("ti_i2c_eeprom_init failed %d\n", rc);
527
528 #ifdef CONFIG_SUPPORT_EMMC_BOOT
529 rc = board_bootmode_has_emmc();
530 if (!rc)
531 rc = ti_emmc_boardid_get();
532 if (rc)
533 printf("ti_emmc_boardid_get failed %d\n", rc);
534 #endif
535 }
536
537 #else /* CONFIG_SPL_BUILD */
538
539 /* Override function to read eeprom information: actual i2c read done by SPL*/
540 void do_board_detect(void)
541 {
542 char *bname = NULL;
543 int rc;
544
545 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
546 CONFIG_EEPROM_CHIP_ADDRESS);
547 if (rc)
548 printf("ti_i2c_eeprom_init failed %d\n", rc);
549
550 #ifdef CONFIG_SUPPORT_EMMC_BOOT
551 rc = board_bootmode_has_emmc();
552 if (!rc)
553 rc = ti_emmc_boardid_get();
554 if (rc)
555 printf("ti_emmc_boardid_get failed %d\n", rc);
556 #endif
557
558 if (board_is_x15())
559 bname = "BeagleBoard X15";
560 else if (board_is_am572x_evm())
561 bname = "AM572x EVM";
562 else if (board_is_am574x_idk())
563 bname = "AM574x IDK";
564 else if (board_is_am572x_idk())
565 bname = "AM572x IDK";
566 else if (board_is_am571x_idk())
567 bname = "AM571x IDK";
568 else if (board_is_bbai())
569 bname = "BeagleBone AI";
570
571 if (bname)
572 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
573 "Board: %s REV %s\n", bname, board_ti_get_rev());
574 }
575
576 static void setup_board_eeprom_env(void)
577 {
578 char *name = "beagle_x15";
579 int rc;
580
581 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
582 CONFIG_EEPROM_CHIP_ADDRESS);
583 if (rc)
584 goto invalid_eeprom;
585
586 if (board_is_x15()) {
587 if (board_is_x15_revb1())
588 name = "beagle_x15_revb1";
589 else if (board_is_x15_revc())
590 name = "beagle_x15_revc";
591 else
592 name = "beagle_x15";
593 } else if (board_is_am572x_evm()) {
594 if (board_is_am572x_evm_reva3())
595 name = "am57xx_evm_reva3";
596 else
597 name = "am57xx_evm";
598 } else if (board_is_am574x_idk()) {
599 name = "am574x_idk";
600 } else if (board_is_am572x_idk()) {
601 name = "am572x_idk";
602 } else if (board_is_am571x_idk()) {
603 name = "am571x_idk";
604 } else if (board_is_bbai()) {
605 name = "am5729_beagleboneai";
606 } else {
607 printf("Unidentified board claims %s in eeprom header\n",
608 board_ti_get_name());
609 }
610
611 invalid_eeprom:
612 set_board_info_env(name);
613 }
614
615 #endif /* CONFIG_SPL_BUILD */
616
617 void vcores_init(void)
618 {
619 if (board_is_am572x_idk() || board_is_am574x_idk())
620 *omap_vcores = &am572x_idk_volts;
621 else if (board_is_am571x_idk())
622 *omap_vcores = &am571x_idk_volts;
623 else
624 *omap_vcores = &beagle_x15_volts;
625 }
626
627 void hw_data_init(void)
628 {
629 *prcm = &dra7xx_prcm;
630 if (is_dra72x())
631 *dplls_data = &dra72x_dplls;
632 else if (is_dra76x())
633 *dplls_data = &dra76x_dplls;
634 else
635 *dplls_data = &dra7xx_dplls;
636 *ctrl = &dra7xx_ctrl;
637 }
638
639 bool am571x_idk_needs_lcd(void)
640 {
641 bool needs_lcd;
642
643 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
644 if (gpio_get_value(GPIO_ETH_LCD))
645 needs_lcd = false;
646 else
647 needs_lcd = true;
648
649 gpio_free(GPIO_ETH_LCD);
650
651 return needs_lcd;
652 }
653
654 int board_init(void)
655 {
656 gpmc_init();
657 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
658
659 return 0;
660 }
661
662 void am57x_idk_lcd_detect(void)
663 {
664 int r = -ENODEV;
665 char *idk_lcd = "no";
666 struct udevice *dev;
667
668 /* Only valid for IDKs */
669 if (board_is_x15() || board_is_am572x_evm() || board_is_bbai())
670 return;
671
672 /* Only AM571x IDK has gpio control detect.. so check that */
673 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
674 goto out;
675
676 r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
677 OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
678 if (r) {
679 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
680 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
681 r);
682 /* AM572x IDK has no explicit settings for optional LCD kit */
683 if (board_is_am571x_idk())
684 printf("%s: Touch screen detect failed: %d!\n",
685 __func__, r);
686 goto out;
687 }
688
689 /* Read FT ID */
690 r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
691 if (r < 0) {
692 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
693 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
694 OSD_TS_FT_REG_ID, r);
695 goto out;
696 }
697
698 switch (r) {
699 case OSD_TS_FT_ID_5606:
700 idk_lcd = "osd101t2045";
701 break;
702 case OSD_TS_FT_ID_5x46:
703 idk_lcd = "osd101t2587";
704 break;
705 default:
706 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
707 __func__, r);
708 /* we will let default be "no lcd" */
709 }
710 out:
711 env_set("idk_lcd", idk_lcd);
712
713 /*
714 * On AM571x_IDK, no Display with J51 set to LCD is considered as an
715 * invalid configuration and we prevent boot to get user attention.
716 */
717 if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
718 !strncmp(idk_lcd, "no", 2)) {
719 printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
720 __func__);
721 hang();
722 }
723
724 return;
725 }
726
727 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
728 static int device_okay(const char *path)
729 {
730 int node;
731
732 node = fdt_path_offset(gd->fdt_blob, path);
733 if (node < 0)
734 return 0;
735
736 return fdtdec_get_is_enabled(gd->fdt_blob, node);
737 }
738 #endif
739
740 int board_late_init(void)
741 {
742 setup_board_eeprom_env();
743 u8 val;
744 struct udevice *dev;
745
746 /*
747 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
748 * This is the POWERHOLD-in-Low behavior.
749 */
750 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
751
752 /*
753 * Default FIT boot on HS devices. Non FIT images are not allowed
754 * on HS devices.
755 */
756 if (get_device_type() == HS_DEVICE)
757 env_set("boot_fit", "1");
758
759 /*
760 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
761 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
762 * PMIC Power off. So to be on the safer side set it back
763 * to POWERHOLD mode irrespective of the current state.
764 */
765 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
766 &val);
767 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
768 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
769 val);
770
771 omap_die_id_serial();
772 omap_set_fastboot_vars();
773
774 am57x_idk_lcd_detect();
775
776 /* Just probe the potentially supported cdce913 device */
777 uclass_get_device(UCLASS_CLK, 0, &dev);
778
779 if (board_is_bbai())
780 env_set("console", "ttyS0,115200n8");
781
782 #if !defined(CONFIG_SPL_BUILD)
783 board_ti_set_ethaddr(2);
784 #endif
785
786 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
787 if (device_okay("/ocp/omap_dwc3_1@48880000"))
788 enable_usb_clocks(0);
789 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
790 enable_usb_clocks(1);
791 #endif
792 return 0;
793 }
794
795 void set_muxconf_regs(void)
796 {
797 do_set_mux32((*ctrl)->control_padconf_core_base,
798 early_padconf, ARRAY_SIZE(early_padconf));
799
800 #ifdef CONFIG_SUPPORT_EMMC_BOOT
801 do_set_mux32((*ctrl)->control_padconf_core_base,
802 emmc_padconf, ARRAY_SIZE(emmc_padconf));
803 #endif
804 }
805
806 #ifdef CONFIG_IODELAY_RECALIBRATION
807 void recalibrate_iodelay(void)
808 {
809 const struct pad_conf_entry *pconf;
810 const struct iodelay_cfg_entry *iod, *delta_iod;
811 int pconf_sz, iod_sz, delta_iod_sz = 0;
812 int ret;
813
814 if (board_is_am572x_idk()) {
815 pconf = core_padconf_array_essential_am572x_idk;
816 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
817 iod = iodelay_cfg_array_am572x_idk;
818 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
819 } else if (board_is_am574x_idk()) {
820 pconf = core_padconf_array_essential_am574x_idk;
821 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
822 iod = iodelay_cfg_array_am574x_idk;
823 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
824 } else if (board_is_am571x_idk()) {
825 pconf = core_padconf_array_essential_am571x_idk;
826 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
827 iod = iodelay_cfg_array_am571x_idk;
828 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
829 } else if (board_is_bbai()) {
830 pconf = core_padconf_array_essential_bbai;
831 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
832 iod = iodelay_cfg_array_bbai;
833 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
834 } else {
835 /* Common for X15/GPEVM */
836 pconf = core_padconf_array_essential_x15;
837 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
838 /* There never was an SR1.0 X15.. So.. */
839 if (omap_revision() == DRA752_ES1_1) {
840 iod = iodelay_cfg_array_x15_sr1_1;
841 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
842 } else {
843 /* Since full production should switch to SR2.0 */
844 iod = iodelay_cfg_array_x15_sr2_0;
845 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
846 }
847 }
848
849 /* Setup I/O isolation */
850 ret = __recalibrate_iodelay_start();
851 if (ret)
852 goto err;
853
854 /* Do the muxing here */
855 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
856
857 /* Now do the weird minor deltas that should be safe */
858 if (board_is_x15() || board_is_am572x_evm()) {
859 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
860 board_is_x15_revc()) {
861 pconf = core_padconf_array_delta_x15_sr2_0;
862 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
863 } else {
864 pconf = core_padconf_array_delta_x15_sr1_1;
865 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
866 }
867 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
868 }
869
870 if (board_is_am571x_idk()) {
871 if (am571x_idk_needs_lcd()) {
872 pconf = core_padconf_array_vout_am571x_idk;
873 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
874 delta_iod = iodelay_cfg_array_am571x_idk_4port;
875 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
876
877 } else {
878 pconf = core_padconf_array_icss1eth_am571x_idk;
879 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
880 }
881 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
882 }
883
884 /* Setup IOdelay configuration */
885 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
886 if (delta_iod_sz)
887 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
888 delta_iod_sz);
889
890 err:
891 /* Closeup.. remove isolation */
892 __recalibrate_iodelay_end(ret);
893 }
894 #endif
895
896 #if defined(CONFIG_MMC)
897 int board_mmc_init(bd_t *bis)
898 {
899 omap_mmc_init(0, 0, 0, -1, -1);
900 omap_mmc_init(1, 0, 0, -1, -1);
901 return 0;
902 }
903
904 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
905 .hw_rev = "rev11",
906 .unsupported_caps = MMC_CAP(MMC_HS_200) |
907 MMC_CAP(UHS_SDR104),
908 .max_freq = 96000000,
909 };
910
911 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
912 .hw_rev = "rev11",
913 .unsupported_caps = MMC_CAP(MMC_HS_200) |
914 MMC_CAP(UHS_SDR104) |
915 MMC_CAP(UHS_SDR50),
916 .max_freq = 48000000,
917 };
918
919 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
920 {
921 switch (omap_revision()) {
922 case DRA752_ES1_0:
923 case DRA752_ES1_1:
924 if (addr == OMAP_HSMMC1_BASE)
925 return &am57x_es1_1_mmc1_fixups;
926 else
927 return &am57x_es1_1_mmc23_fixups;
928 default:
929 return NULL;
930 }
931 }
932 #endif
933
934 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
935 int spl_start_uboot(void)
936 {
937 /* break into full u-boot on 'c' */
938 if (serial_tstc() && serial_getc() == 'c')
939 return 1;
940
941 #ifdef CONFIG_SPL_ENV_SUPPORT
942 env_init();
943 env_load();
944 if (env_get_yesno("boot_os") != 1)
945 return 1;
946 #endif
947
948 return 0;
949 }
950 #endif
951
952 #ifdef CONFIG_DRIVER_TI_CPSW
953
954 /* Delay value to add to calibrated value */
955 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
956 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
957 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
958 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
959 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
960 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
961 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
962 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
963 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
964 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
965
966 static void cpsw_control(int enabled)
967 {
968 /* VTP can be added here */
969 }
970
971 static struct cpsw_slave_data cpsw_slaves[] = {
972 {
973 .slave_reg_ofs = 0x208,
974 .sliver_reg_ofs = 0xd80,
975 .phy_addr = 1,
976 },
977 {
978 .slave_reg_ofs = 0x308,
979 .sliver_reg_ofs = 0xdc0,
980 .phy_addr = 2,
981 },
982 };
983
984 static struct cpsw_platform_data cpsw_data = {
985 .mdio_base = CPSW_MDIO_BASE,
986 .cpsw_base = CPSW_BASE,
987 .mdio_div = 0xff,
988 .channels = 8,
989 .cpdma_reg_ofs = 0x800,
990 .slaves = 1,
991 .slave_data = cpsw_slaves,
992 .ale_reg_ofs = 0xd00,
993 .ale_entries = 1024,
994 .host_port_reg_ofs = 0x108,
995 .hw_stats_reg_ofs = 0x900,
996 .bd_ram_ofs = 0x2000,
997 .mac_control = (1 << 5),
998 .control = cpsw_control,
999 .host_port_num = 0,
1000 .version = CPSW_CTRL_VERSION_2,
1001 };
1002
1003 static u64 mac_to_u64(u8 mac[6])
1004 {
1005 int i;
1006 u64 addr = 0;
1007
1008 for (i = 0; i < 6; i++) {
1009 addr <<= 8;
1010 addr |= mac[i];
1011 }
1012
1013 return addr;
1014 }
1015
1016 static void u64_to_mac(u64 addr, u8 mac[6])
1017 {
1018 mac[5] = addr;
1019 mac[4] = addr >> 8;
1020 mac[3] = addr >> 16;
1021 mac[2] = addr >> 24;
1022 mac[1] = addr >> 32;
1023 mac[0] = addr >> 40;
1024 }
1025
1026 int board_eth_init(bd_t *bis)
1027 {
1028 int ret;
1029 uint8_t mac_addr[6];
1030 uint32_t mac_hi, mac_lo;
1031 uint32_t ctrl_val;
1032 int i;
1033 u64 mac1, mac2;
1034 u8 mac_addr1[6], mac_addr2[6];
1035 int num_macs;
1036
1037 /* try reading mac address from efuse */
1038 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1039 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1040 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1041 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1042 mac_addr[2] = mac_hi & 0xFF;
1043 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1044 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1045 mac_addr[5] = mac_lo & 0xFF;
1046
1047 if (!env_get("ethaddr")) {
1048 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1049
1050 if (is_valid_ethaddr(mac_addr))
1051 eth_env_set_enetaddr("ethaddr", mac_addr);
1052 }
1053
1054 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1055 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1056 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1057 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1058 mac_addr[2] = mac_hi & 0xFF;
1059 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1060 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1061 mac_addr[5] = mac_lo & 0xFF;
1062
1063 if (!env_get("eth1addr")) {
1064 if (is_valid_ethaddr(mac_addr))
1065 eth_env_set_enetaddr("eth1addr", mac_addr);
1066 }
1067
1068 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1069 ctrl_val |= 0x22;
1070 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1071
1072 /* The phy address for the AM57xx IDK are different than x15 */
1073 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1074 board_is_am574x_idk()) {
1075 cpsw_data.slave_data[0].phy_addr = 0;
1076 cpsw_data.slave_data[1].phy_addr = 1;
1077 }
1078
1079 ret = cpsw_register(&cpsw_data);
1080 if (ret < 0)
1081 printf("Error %d registering CPSW switch\n", ret);
1082
1083 /*
1084 * Export any Ethernet MAC addresses from EEPROM.
1085 * On AM57xx the 2 MAC addresses define the address range
1086 */
1087 board_ti_get_eth_mac_addr(0, mac_addr1);
1088 board_ti_get_eth_mac_addr(1, mac_addr2);
1089
1090 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1091 mac1 = mac_to_u64(mac_addr1);
1092 mac2 = mac_to_u64(mac_addr2);
1093
1094 /* must contain an address range */
1095 num_macs = mac2 - mac1 + 1;
1096 /* <= 50 to protect against user programming error */
1097 if (num_macs > 0 && num_macs <= 50) {
1098 for (i = 0; i < num_macs; i++) {
1099 u64_to_mac(mac1 + i, mac_addr);
1100 if (is_valid_ethaddr(mac_addr)) {
1101 eth_env_set_enetaddr_by_index("eth",
1102 i + 2,
1103 mac_addr);
1104 }
1105 }
1106 }
1107 }
1108
1109 return ret;
1110 }
1111 #endif
1112
1113 #ifdef CONFIG_BOARD_EARLY_INIT_F
1114 /* VTT regulator enable */
1115 static inline void vtt_regulator_enable(void)
1116 {
1117 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1118 return;
1119
1120 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1121 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1122 }
1123
1124 int board_early_init_f(void)
1125 {
1126 vtt_regulator_enable();
1127 return 0;
1128 }
1129 #endif
1130
1131 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1132 int ft_board_setup(void *blob, bd_t *bd)
1133 {
1134 ft_cpu_setup(blob, bd);
1135
1136 return 0;
1137 }
1138 #endif
1139
1140 #ifdef CONFIG_SPL_LOAD_FIT
1141 int board_fit_config_name_match(const char *name)
1142 {
1143 if (board_is_x15()) {
1144 if (board_is_x15_revb1()) {
1145 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1146 return 0;
1147 } else if (board_is_x15_revc()) {
1148 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1149 return 0;
1150 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1151 return 0;
1152 }
1153 } else if (board_is_am572x_evm() &&
1154 !strcmp(name, "am57xx-beagle-x15")) {
1155 return 0;
1156 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1157 return 0;
1158 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1159 return 0;
1160 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1161 return 0;
1162 } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1163 return 0;
1164 }
1165
1166 return -1;
1167 }
1168 #endif
1169
1170 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1171 int fastboot_set_reboot_flag(void)
1172 {
1173 printf("Setting reboot to fastboot flag ...\n");
1174 env_set("dofastboot", "1");
1175 env_save();
1176 return 0;
1177 }
1178 #endif
1179
1180 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1181 static int board_bootmode_has_emmc(void)
1182 {
1183 /* Check that boot mode is same as BBAI */
1184 if (gd->arch.omap_boot_mode != 2)
1185 return -EIO;
1186
1187 return 0;
1188 }
1189 #endif
1190
1191 #ifdef CONFIG_TI_SECURE_DEVICE
1192 void board_fit_image_post_process(void **p_image, size_t *p_size)
1193 {
1194 secure_boot_verify_image(p_image, p_size);
1195 }
1196
1197 void board_tee_image_process(ulong tee_image, size_t tee_size)
1198 {
1199 secure_tee_install((u32)tee_image);
1200 }
1201
1202 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1203 #endif
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