board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/emif.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/omap.h>
  26 #include <environment.h>
  27 #include <usb.h>
  28 #include <linux/usb/gadget.h>
  29 #include <dwc3-uboot.h>
  30 #include <dwc3-omap-uboot.h>
  31 #include <ti-usb-phy-uboot.h>
  32
  33 #include "../common/board_detect.h"
  34 #include "mux_data.h"
  35
  36 #define board_is_x15()          board_ti_is("BBRDX15_")
  37 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  38 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  39
  40 #ifdef CONFIG_DRIVER_TI_CPSW
  41 #include <cpsw.h>
  42 #endif
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO 7_11 */
  47 #define GPIO_DDR_VTT_EN 203
  48
  49 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  50
  51 const struct omap_sysinfo sysinfo = {
  52         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  53 };
  54
  55 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  56         .dmm_lisa_map_3 = 0x80740300,
  57         .is_ma_present  = 0x1
  58 };
  59
  60 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  61 {
  62         *dmm_lisa_regs = &beagle_x15_lisa_regs;
  63 }
  64
  65 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  66         .sdram_config_init      = 0x61851b32,
  67         .sdram_config           = 0x61851b32,
  68         .sdram_config2          = 0x08000000,
  69         .ref_ctrl               = 0x000040F1,
  70         .ref_ctrl_final         = 0x00001035,
  71         .sdram_tim1             = 0xcccf36ab,
  72         .sdram_tim2             = 0x308f7fda,
  73         .sdram_tim3             = 0x409f88a8,
  74         .read_idle_ctrl         = 0x00050000,
  75         .zq_config              = 0x5007190b,
  76         .temp_alert_config      = 0x00000000,
  77         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  78         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
  79         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  80         .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  81         .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  82         .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  83         .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  84         .emif_rd_wr_lvl_rmp_win = 0x00000000,
  85         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  86         .emif_rd_wr_lvl_ctl     = 0x00000000,
  87         .emif_rd_wr_exec_thresh = 0x00000305
  88 };
  89
  90 /* Ext phy ctrl regs 1-35 */
  91 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  92         0x10040100,
  93         0x00910091,
  94         0x00950095,
  95         0x009B009B,
  96         0x009E009E,
  97         0x00980098,
  98         0x00340034,
  99         0x00350035,
 100         0x00340034,
 101         0x00310031,
 102         0x00340034,
 103         0x007F007F,
 104         0x007F007F,
 105         0x007F007F,
 106         0x007F007F,
 107         0x007F007F,
 108         0x00480048,
 109         0x004A004A,
 110         0x00520052,
 111         0x00550055,
 112         0x00500050,
 113         0x00000000,
 114         0x00600020,
 115         0x40011080,
 116         0x08102040,
 117         0x0,
 118         0x0,
 119         0x0,
 120         0x0,
 121         0x0,
 122         0x0,
 123         0x0,
 124         0x0,
 125         0x0,
 126         0x0
 127 };
 128
 129 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 130         .sdram_config_init      = 0x61851b32,
 131         .sdram_config           = 0x61851b32,
 132         .sdram_config2          = 0x08000000,
 133         .ref_ctrl               = 0x000040F1,
 134         .ref_ctrl_final         = 0x00001035,
 135         .sdram_tim1             = 0xcccf36b3,
 136         .sdram_tim2             = 0x308f7fda,
 137         .sdram_tim3             = 0x407f88a8,
 138         .read_idle_ctrl         = 0x00050000,
 139         .zq_config              = 0x5007190b,
 140         .temp_alert_config      = 0x00000000,
 141         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
 142         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
 143         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
 144         .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
 145         .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
 146         .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
 147         .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
 148         .emif_rd_wr_lvl_rmp_win = 0x00000000,
 149         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
 150         .emif_rd_wr_lvl_ctl     = 0x00000000,
 151         .emif_rd_wr_exec_thresh = 0x00000305
 152 };
 153
 154 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 155         0x10040100,
 156         0x00910091,
 157         0x00950095,
 158         0x009B009B,
 159         0x009E009E,
 160         0x00980098,
 161         0x00340034,
 162         0x00350035,
 163         0x00340034,
 164         0x00310031,
 165         0x00340034,
 166         0x007F007F,
 167         0x007F007F,
 168         0x007F007F,
 169         0x007F007F,
 170         0x007F007F,
 171         0x00480048,
 172         0x004A004A,
 173         0x00520052,
 174         0x00550055,
 175         0x00500050,
 176         0x00000000,
 177         0x00600020,
 178         0x40011080,
 179         0x08102040,
 180         0x0,
 181         0x0,
 182         0x0,
 183         0x0,
 184         0x0,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0
 190 };
 191
 192 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 193 {
 194         switch (emif_nr) {
 195         case 1:
 196                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 197                 break;
 198         case 2:
 199                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 200                 break;
 201         }
 202 }
 203
 204 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 205 {
 206         switch (emif_nr) {
 207         case 1:
 208                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 209                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 210                 break;
 211         case 2:
 212                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 213                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 214                 break;
 215         }
 216 }
 217
 218 struct vcores_data beagle_x15_volts = {
 219         .mpu.value              = VDD_MPU_DRA7,
 220         .mpu.efuse.reg          = STD_FUSE_OPP_VMIN_MPU,
 221         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 222         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 223         .mpu.pmic               = &tps659038,
 224         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 225
 226         .eve.value              = VDD_EVE_DRA7,
 227         .eve.efuse.reg          = STD_FUSE_OPP_VMIN_DSPEVE,
 228         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 229         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 230         .eve.pmic               = &tps659038,
 231         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 232
 233         .gpu.value              = VDD_GPU_DRA7,
 234         .gpu.efuse.reg          = STD_FUSE_OPP_VMIN_GPU,
 235         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 236         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 237         .gpu.pmic               = &tps659038,
 238         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 239
 240         .core.value             = VDD_CORE_DRA7,
 241         .core.efuse.reg         = STD_FUSE_OPP_VMIN_CORE,
 242         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 243         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 244         .core.pmic              = &tps659038,
 245
 246         .iva.value              = VDD_IVA_DRA7,
 247         .iva.efuse.reg          = STD_FUSE_OPP_VMIN_IVA,
 248         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 249         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 250         .iva.pmic               = &tps659038,
 251         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 252 };
 253
 254 #ifdef CONFIG_SPL_BUILD
 255 /* No env to setup for SPL */
 256 static inline void setup_board_eeprom_env(void) { }
 257
 258 /* Override function to read eeprom information */
 259 void do_board_detect(void)
 260 {
 261         int rc;
 262
 263         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 264                                   CONFIG_EEPROM_CHIP_ADDRESS);
 265         if (rc)
 266                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 267 }
 268
 269 #else   /* CONFIG_SPL_BUILD */
 270
 271 /* Override function to read eeprom information: actual i2c read done by SPL*/
 272 void do_board_detect(void)
 273 {
 274         char *bname = NULL;
 275         int rc;
 276
 277         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 278                                   CONFIG_EEPROM_CHIP_ADDRESS);
 279         if (rc)
 280                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 281
 282         if (board_is_x15())
 283                 bname = "BeagleBoard X15";
 284         else if (board_is_am572x_evm())
 285                 bname = "AM572x EVM";
 286         else if (board_is_am572x_idk())
 287                 bname = "AM572x IDK";
 288
 289         if (bname)
 290                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 291                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 292 }
 293
 294 static void setup_board_eeprom_env(void)
 295 {
 296         char *name = "beagle_x15";
 297         int rc;
 298
 299         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 300                                   CONFIG_EEPROM_CHIP_ADDRESS);
 301         if (rc)
 302                 goto invalid_eeprom;
 303
 304         if (board_is_am572x_evm())
 305                 name = "am57xx_evm";
 306         else if (board_is_am572x_idk())
 307                 name = "am572x_idk";
 308         else
 309                 printf("Unidentified board claims %s in eeprom header\n",
 310                        board_ti_get_name());
 311
 312 invalid_eeprom:
 313         set_board_info_env(name);
 314 }
 315
 316 #endif  /* CONFIG_SPL_BUILD */
 317
 318 void hw_data_init(void)
 319 {
 320         *prcm = &dra7xx_prcm;
 321         *dplls_data = &dra7xx_dplls;
 322         *omap_vcores = &beagle_x15_volts;
 323         *ctrl = &dra7xx_ctrl;
 324 }
 325
 326 int board_init(void)
 327 {
 328         gpmc_init();
 329         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 330
 331         return 0;
 332 }
 333
 334 int board_late_init(void)
 335 {
 336         setup_board_eeprom_env();
 337
 338         /*
 339          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 340          * This is the POWERHOLD-in-Low behavior.
 341          */
 342         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 343         return 0;
 344 }
 345
 346 void set_muxconf_regs(void)
 347 {
 348         do_set_mux32((*ctrl)->control_padconf_core_base,
 349                      early_padconf, ARRAY_SIZE(early_padconf));
 350 }
 351
 352 #ifdef CONFIG_IODELAY_RECALIBRATION
 353 void recalibrate_iodelay(void)
 354 {
 355         const struct pad_conf_entry *pconf;
 356         const struct iodelay_cfg_entry *iod;
 357         int pconf_sz, iod_sz;
 358
 359         if (board_is_am572x_idk()) {
 360                 pconf = core_padconf_array_essential_am572x_idk;
 361                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 362                 iod = iodelay_cfg_array_am572x_idk;
 363                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 364         } else {
 365                 /* Common for X15/GPEVM */
 366                 pconf = core_padconf_array_essential_x15;
 367                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 368                 iod = iodelay_cfg_array_x15;
 369                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
 370         }
 371
 372         __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 373 }
 374 #endif
 375
 376 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 377 int board_mmc_init(bd_t *bis)
 378 {
 379         omap_mmc_init(0, 0, 0, -1, -1);
 380         omap_mmc_init(1, 0, 0, -1, -1);
 381         return 0;
 382 }
 383 #endif
 384
 385 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 386 int spl_start_uboot(void)
 387 {
 388         /* break into full u-boot on 'c' */
 389         if (serial_tstc() && serial_getc() == 'c')
 390                 return 1;
 391
 392 #ifdef CONFIG_SPL_ENV_SUPPORT
 393         env_init();
 394         env_relocate_spec();
 395         if (getenv_yesno("boot_os") != 1)
 396                 return 1;
 397 #endif
 398
 399         return 0;
 400 }
 401 #endif
 402
 403 #ifdef CONFIG_USB_DWC3
 404 static struct dwc3_device usb_otg_ss1 = {
 405         .maximum_speed = USB_SPEED_SUPER,
 406         .base = DRA7_USB_OTG_SS1_BASE,
 407         .tx_fifo_resize = false,
 408         .index = 0,
 409 };
 410
 411 static struct dwc3_omap_device usb_otg_ss1_glue = {
 412         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 413         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 414         .index = 0,
 415 };
 416
 417 static struct ti_usb_phy_device usb_phy1_device = {
 418         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 419         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 420         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 421         .index = 0,
 422 };
 423
 424 static struct dwc3_device usb_otg_ss2 = {
 425         .maximum_speed = USB_SPEED_HIGH,
 426         .base = DRA7_USB_OTG_SS2_BASE,
 427         .tx_fifo_resize = false,
 428         .index = 1,
 429 };
 430
 431 static struct dwc3_omap_device usb_otg_ss2_glue = {
 432         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 433         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 434         .index = 1,
 435 };
 436
 437 static struct ti_usb_phy_device usb_phy2_device = {
 438         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 439         .index = 1,
 440 };
 441
 442 int usb_gadget_handle_interrupts(int index)
 443 {
 444         u32 status;
 445
 446         status = dwc3_omap_uboot_interrupt_status(index);
 447         if (status)
 448                 dwc3_uboot_handle_interrupt(index);
 449
 450         return 0;
 451 }
 452 #endif /* CONFIG_USB_DWC3 */
 453
 454 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 455 int board_usb_init(int index, enum usb_init_type init)
 456 {
 457         enable_usb_clocks(index);
 458         switch (index) {
 459         case 0:
 460                 if (init == USB_INIT_DEVICE) {
 461                         printf("port %d can't be used as device\n", index);
 462                         disable_usb_clocks(index);
 463                         return -EINVAL;
 464                 }
 465                 break;
 466         case 1:
 467                 if (init == USB_INIT_DEVICE) {
 468 #ifdef CONFIG_USB_DWC3
 469                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 470                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 471                         ti_usb_phy_uboot_init(&usb_phy2_device);
 472                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 473                         dwc3_uboot_init(&usb_otg_ss2);
 474 #endif
 475                 } else {
 476                         printf("port %d can't be used as host\n", index);
 477                         disable_usb_clocks(index);
 478                         return -EINVAL;
 479                 }
 480
 481                 break;
 482         default:
 483                 printf("Invalid Controller Index\n");
 484         }
 485
 486         return 0;
 487 }
 488
 489 int board_usb_cleanup(int index, enum usb_init_type init)
 490 {
 491 #ifdef CONFIG_USB_DWC3
 492         switch (index) {
 493         case 0:
 494         case 1:
 495                 if (init == USB_INIT_DEVICE) {
 496                         ti_usb_phy_uboot_exit(index);
 497                         dwc3_uboot_exit(index);
 498                         dwc3_omap_uboot_exit(index);
 499                 }
 500                 break;
 501         default:
 502                 printf("Invalid Controller Index\n");
 503         }
 504 #endif
 505         disable_usb_clocks(index);
 506         return 0;
 507 }
 508 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 509
 510 #ifdef CONFIG_DRIVER_TI_CPSW
 511
 512 /* Delay value to add to calibrated value */
 513 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 514 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 515 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 516 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 517 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 518 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 519 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 520 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 521 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 522 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 523
 524 static void cpsw_control(int enabled)
 525 {
 526         /* VTP can be added here */
 527 }
 528
 529 static struct cpsw_slave_data cpsw_slaves[] = {
 530         {
 531                 .slave_reg_ofs  = 0x208,
 532                 .sliver_reg_ofs = 0xd80,
 533                 .phy_addr       = 1,
 534         },
 535         {
 536                 .slave_reg_ofs  = 0x308,
 537                 .sliver_reg_ofs = 0xdc0,
 538                 .phy_addr       = 2,
 539         },
 540 };
 541
 542 static struct cpsw_platform_data cpsw_data = {
 543         .mdio_base              = CPSW_MDIO_BASE,
 544         .cpsw_base              = CPSW_BASE,
 545         .mdio_div               = 0xff,
 546         .channels               = 8,
 547         .cpdma_reg_ofs          = 0x800,
 548         .slaves                 = 1,
 549         .slave_data             = cpsw_slaves,
 550         .ale_reg_ofs            = 0xd00,
 551         .ale_entries            = 1024,
 552         .host_port_reg_ofs      = 0x108,
 553         .hw_stats_reg_ofs       = 0x900,
 554         .bd_ram_ofs             = 0x2000,
 555         .mac_control            = (1 << 5),
 556         .control                = cpsw_control,
 557         .host_port_num          = 0,
 558         .version                = CPSW_CTRL_VERSION_2,
 559 };
 560
 561 static u64 mac_to_u64(u8 mac[6])
 562 {
 563         int i;
 564         u64 addr = 0;
 565
 566         for (i = 0; i < 6; i++) {
 567                 addr <<= 8;
 568                 addr |= mac[i];
 569         }
 570
 571         return addr;
 572 }
 573
 574 static void u64_to_mac(u64 addr, u8 mac[6])
 575 {
 576         mac[5] = addr;
 577         mac[4] = addr >> 8;
 578         mac[3] = addr >> 16;
 579         mac[2] = addr >> 24;
 580         mac[1] = addr >> 32;
 581         mac[0] = addr >> 40;
 582 }
 583
 584 int board_eth_init(bd_t *bis)
 585 {
 586         int ret;
 587         uint8_t mac_addr[6];
 588         uint32_t mac_hi, mac_lo;
 589         uint32_t ctrl_val;
 590         int i;
 591         u64 mac1, mac2;
 592         u8 mac_addr1[6], mac_addr2[6];
 593         int num_macs;
 594
 595         /* try reading mac address from efuse */
 596         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 597         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 598         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 599         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 600         mac_addr[2] = mac_hi & 0xFF;
 601         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 602         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 603         mac_addr[5] = mac_lo & 0xFF;
 604
 605         if (!getenv("ethaddr")) {
 606                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 607
 608                 if (is_valid_ethaddr(mac_addr))
 609                         eth_setenv_enetaddr("ethaddr", mac_addr);
 610         }
 611
 612         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 613         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 614         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 615         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 616         mac_addr[2] = mac_hi & 0xFF;
 617         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 618         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 619         mac_addr[5] = mac_lo & 0xFF;
 620
 621         if (!getenv("eth1addr")) {
 622                 if (is_valid_ethaddr(mac_addr))
 623                         eth_setenv_enetaddr("eth1addr", mac_addr);
 624         }
 625
 626         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 627         ctrl_val |= 0x22;
 628         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 629
 630         /* The phy address for the AM572x IDK are different than x15 */
 631         if (board_is_am572x_idk()) {
 632                 cpsw_data.slave_data[0].phy_addr = 0;
 633                 cpsw_data.slave_data[1].phy_addr = 1;
 634         }
 635
 636         ret = cpsw_register(&cpsw_data);
 637         if (ret < 0)
 638                 printf("Error %d registering CPSW switch\n", ret);
 639
 640         /*
 641          * Export any Ethernet MAC addresses from EEPROM.
 642          * On AM57xx the 2 MAC addresses define the address range
 643          */
 644         board_ti_get_eth_mac_addr(0, mac_addr1);
 645         board_ti_get_eth_mac_addr(1, mac_addr2);
 646
 647         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 648                 mac1 = mac_to_u64(mac_addr1);
 649                 mac2 = mac_to_u64(mac_addr2);
 650
 651                 /* must contain an address range */
 652                 num_macs = mac2 - mac1 + 1;
 653                 /* <= 50 to protect against user programming error */
 654                 if (num_macs > 0 && num_macs <= 50) {
 655                         for (i = 0; i < num_macs; i++) {
 656                                 u64_to_mac(mac1 + i, mac_addr);
 657                                 if (is_valid_ethaddr(mac_addr)) {
 658                                         eth_setenv_enetaddr_by_index("eth",
 659                                                                      i + 2,
 660                                                                      mac_addr);
 661                                 }
 662                         }
 663                 }
 664         }
 665
 666         return ret;
 667 }
 668 #endif
 669
 670 #ifdef CONFIG_BOARD_EARLY_INIT_F
 671 /* VTT regulator enable */
 672 static inline void vtt_regulator_enable(void)
 673 {
 674         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 675                 return;
 676
 677         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 678         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 679 }
 680
 681 int board_early_init_f(void)
 682 {
 683         vtt_regulator_enable();
 684         return 0;
 685 }
 686 #endif
 687
 688 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 689 int ft_board_setup(void *blob, bd_t *bd)
 690 {
 691         ft_cpu_setup(blob, bd);
 692
 693         return 0;
 694 }
 695 #endif