board/ti/beagle/beagle.h

   1 /*
   2  * (C) Copyright 2008
   3  * Dirk Behme <dirk.behme@gmail.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #ifndef _BEAGLE_H_
  24 #define _BEAGLE_H_
  25
  26 const omap3_sysinfo sysinfo = {
  27         DDR_STACKED,
  28         "OMAP3 Beagle board",
  29 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  30         "OneNAND",
  31 #else
  32         "NAND",
  33 #endif
  34 };
  35
  36 #define BOARD_REVISION_MASK     (0x1 << 11)
  37
  38 /*
  39  * IEN  - Input Enable
  40  * IDIS - Input Disable
  41  * PTD  - Pull type Down
  42  * PTU  - Pull type Up
  43  * DIS  - Pull type selection is inactive
  44  * EN   - Pull type selection is active
  45  * M0   - Mode 0
  46  * The commented string gives the final mux configuration for that pin
  47  */
  48 #define MUX_BEAGLE() \
  49  /*SDRC*/\
  50  MUX_VAL(CP(SDRC_D0),           (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
  51  MUX_VAL(CP(SDRC_D1),           (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
  52  MUX_VAL(CP(SDRC_D2),           (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
  53  MUX_VAL(CP(SDRC_D3),           (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
  54  MUX_VAL(CP(SDRC_D4),           (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
  55  MUX_VAL(CP(SDRC_D5),           (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
  56  MUX_VAL(CP(SDRC_D6),           (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
  57  MUX_VAL(CP(SDRC_D7),           (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
  58  MUX_VAL(CP(SDRC_D8),           (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
  59  MUX_VAL(CP(SDRC_D9),           (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
  60  MUX_VAL(CP(SDRC_D10),          (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
  61  MUX_VAL(CP(SDRC_D11),          (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
  62  MUX_VAL(CP(SDRC_D12),          (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
  63  MUX_VAL(CP(SDRC_D13),          (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
  64  MUX_VAL(CP(SDRC_D14),          (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
  65  MUX_VAL(CP(SDRC_D15),          (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
  66  MUX_VAL(CP(SDRC_D16),          (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
  67  MUX_VAL(CP(SDRC_D17),          (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
  68  MUX_VAL(CP(SDRC_D18),          (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
  69  MUX_VAL(CP(SDRC_D19),          (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
  70  MUX_VAL(CP(SDRC_D20),          (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
  71  MUX_VAL(CP(SDRC_D21),          (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
  72  MUX_VAL(CP(SDRC_D22),          (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
  73  MUX_VAL(CP(SDRC_D23),          (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
  74  MUX_VAL(CP(SDRC_D24),          (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
  75  MUX_VAL(CP(SDRC_D25),          (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
  76  MUX_VAL(CP(SDRC_D26),          (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
  77  MUX_VAL(CP(SDRC_D27),          (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
  78  MUX_VAL(CP(SDRC_D28),          (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
  79  MUX_VAL(CP(SDRC_D29),          (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
  80  MUX_VAL(CP(SDRC_D30),          (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
  81  MUX_VAL(CP(SDRC_D31),          (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
  82  MUX_VAL(CP(SDRC_CLK),          (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
  83  MUX_VAL(CP(SDRC_DQS0),         (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
  84  MUX_VAL(CP(SDRC_DQS1),         (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
  85  MUX_VAL(CP(SDRC_DQS2),         (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
  86  MUX_VAL(CP(SDRC_DQS3),         (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
  87  /*GPMC*/\
  88  MUX_VAL(CP(GPMC_A1),           (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
  89  MUX_VAL(CP(GPMC_A2),           (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
  90  MUX_VAL(CP(GPMC_A3),           (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
  91  MUX_VAL(CP(GPMC_A4),           (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
  92  MUX_VAL(CP(GPMC_A5),           (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
  93  MUX_VAL(CP(GPMC_A6),           (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
  94  MUX_VAL(CP(GPMC_A7),           (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
  95  MUX_VAL(CP(GPMC_A8),           (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
  96  MUX_VAL(CP(GPMC_A9),           (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
  97  MUX_VAL(CP(GPMC_A10),          (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
  98  MUX_VAL(CP(GPMC_D0),           (IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
  99  MUX_VAL(CP(GPMC_D1),           (IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
 100  MUX_VAL(CP(GPMC_D2),           (IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
 101  MUX_VAL(CP(GPMC_D3),           (IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
 102  MUX_VAL(CP(GPMC_D4),           (IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
 103  MUX_VAL(CP(GPMC_D5),           (IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
 104  MUX_VAL(CP(GPMC_D6),           (IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
 105  MUX_VAL(CP(GPMC_D7),           (IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
 106  MUX_VAL(CP(GPMC_D8),           (IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
 107  MUX_VAL(CP(GPMC_D9),           (IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
 108  MUX_VAL(CP(GPMC_D10),          (IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
 109  MUX_VAL(CP(GPMC_D11),          (IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
 110  MUX_VAL(CP(GPMC_D12),          (IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
 111  MUX_VAL(CP(GPMC_D13),          (IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
 112  MUX_VAL(CP(GPMC_D14),          (IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
 113  MUX_VAL(CP(GPMC_D15),          (IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
 114  MUX_VAL(CP(GPMC_NCS0),         (IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
 115  MUX_VAL(CP(GPMC_NCS1),         (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
 116  MUX_VAL(CP(GPMC_NCS2),         (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
 117  MUX_VAL(CP(GPMC_NCS3),         (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
 118  MUX_VAL(CP(GPMC_NCS4),         (IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
 119  MUX_VAL(CP(GPMC_NCS5),         (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
 120  MUX_VAL(CP(GPMC_NCS6),         (IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
 121  MUX_VAL(CP(GPMC_NCS7),         (IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
 122  MUX_VAL(CP(GPMC_NBE1),         (IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
 123  MUX_VAL(CP(GPMC_WAIT2),        (IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
 124  MUX_VAL(CP(GPMC_WAIT3),        (IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
 125  MUX_VAL(CP(GPMC_CLK),          (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
 126  MUX_VAL(CP(GPMC_NADV_ALE),     (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 127  MUX_VAL(CP(GPMC_NOE),          (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
 128  MUX_VAL(CP(GPMC_NWE),          (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
 129  MUX_VAL(CP(GPMC_NBE0_CLE),     (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
 130  MUX_VAL(CP(GPMC_NWP),          (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 131  MUX_VAL(CP(GPMC_WAIT0),        (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
 132  MUX_VAL(CP(GPMC_WAIT1),        (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
 133  /*DSS*/\
 134  MUX_VAL(CP(DSS_PCLK),          (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
 135  MUX_VAL(CP(DSS_HSYNC),         (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
 136  MUX_VAL(CP(DSS_VSYNC),         (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
 137  MUX_VAL(CP(DSS_ACBIAS),        (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
 138  MUX_VAL(CP(DSS_DATA0),         (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
 139  MUX_VAL(CP(DSS_DATA1),         (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
 140  MUX_VAL(CP(DSS_DATA2),         (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
 141  MUX_VAL(CP(DSS_DATA3),         (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
 142  MUX_VAL(CP(DSS_DATA4),         (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
 143  MUX_VAL(CP(DSS_DATA5),         (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
 144  MUX_VAL(CP(DSS_DATA6),         (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
 145  MUX_VAL(CP(DSS_DATA7),         (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
 146  MUX_VAL(CP(DSS_DATA8),         (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
 147  MUX_VAL(CP(DSS_DATA9),         (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
 148  MUX_VAL(CP(DSS_DATA10),        (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
 149  MUX_VAL(CP(DSS_DATA11),        (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
 150  MUX_VAL(CP(DSS_DATA12),        (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
 151  MUX_VAL(CP(DSS_DATA13),        (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
 152  MUX_VAL(CP(DSS_DATA14),        (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
 153  MUX_VAL(CP(DSS_DATA15),        (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
 154  MUX_VAL(CP(DSS_DATA16),        (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
 155  MUX_VAL(CP(DSS_DATA17),        (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
 156  MUX_VAL(CP(DSS_DATA18),        (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
 157  MUX_VAL(CP(DSS_DATA19),        (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
 158  MUX_VAL(CP(DSS_DATA20),        (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
 159  MUX_VAL(CP(DSS_DATA21),        (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
 160  MUX_VAL(CP(DSS_DATA22),        (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
 161  MUX_VAL(CP(DSS_DATA23),        (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
 162  /*CAMERA*/\
 163  MUX_VAL(CP(CAM_HS),            (IEN  | PTU | EN  | M0)) /*CAM_HS */\
 164  MUX_VAL(CP(CAM_VS),            (IEN  | PTU | EN  | M0)) /*CAM_VS */\
 165  MUX_VAL(CP(CAM_XCLKA),         (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
 166  MUX_VAL(CP(CAM_PCLK),          (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
 167  MUX_VAL(CP(CAM_FLD),           (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
 168  MUX_VAL(CP(CAM_D0),            (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
 169  MUX_VAL(CP(CAM_D1),            (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
 170  MUX_VAL(CP(CAM_D2),            (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
 171  MUX_VAL(CP(CAM_D3),            (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
 172  MUX_VAL(CP(CAM_D4),            (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
 173  MUX_VAL(CP(CAM_D5),            (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
 174  MUX_VAL(CP(CAM_D6),            (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
 175  MUX_VAL(CP(CAM_D7),            (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
 176  MUX_VAL(CP(CAM_D8),            (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
 177  MUX_VAL(CP(CAM_D9),            (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
 178  MUX_VAL(CP(CAM_D10),           (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
 179  MUX_VAL(CP(CAM_D11),           (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
 180  MUX_VAL(CP(CAM_XCLKB),         (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
 181  MUX_VAL(CP(CAM_WEN),           (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 182  MUX_VAL(CP(CAM_STROBE),        (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
 183  MUX_VAL(CP(CSI2_DX0),          (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
 184  MUX_VAL(CP(CSI2_DY0),          (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
 185  MUX_VAL(CP(CSI2_DX1),          (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
 186  MUX_VAL(CP(CSI2_DY1),          (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
 187  /*Audio Interface */\
 188  MUX_VAL(CP(MCBSP2_FSX),        (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
 189  MUX_VAL(CP(MCBSP2_CLKX),       (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
 190  MUX_VAL(CP(MCBSP2_DR),         (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
 191  MUX_VAL(CP(MCBSP2_DX),         (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
 192  /*Expansion card */\
 193  MUX_VAL(CP(MMC1_CLK),          (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
 194  MUX_VAL(CP(MMC1_CMD),          (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
 195  MUX_VAL(CP(MMC1_DAT0),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
 196  MUX_VAL(CP(MMC1_DAT1),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
 197  MUX_VAL(CP(MMC1_DAT2),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
 198  MUX_VAL(CP(MMC1_DAT3),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
 199  MUX_VAL(CP(MMC1_DAT4),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
 200  MUX_VAL(CP(MMC1_DAT5),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
 201  MUX_VAL(CP(MMC1_DAT6),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
 202  MUX_VAL(CP(MMC1_DAT7),         (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
 203  /*Wireless LAN */\
 204  MUX_VAL(CP(MMC2_CLK),          (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
 205  MUX_VAL(CP(MMC2_CMD),          (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
 206  MUX_VAL(CP(MMC2_DAT0),         (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
 207  MUX_VAL(CP(MMC2_DAT1),         (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
 208  MUX_VAL(CP(MMC2_DAT2),         (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
 209  MUX_VAL(CP(MMC2_DAT3),         (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
 210  MUX_VAL(CP(MMC2_DAT4),         (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
 211  MUX_VAL(CP(MMC2_DAT5),         (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
 212  MUX_VAL(CP(MMC2_DAT6),         (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
 213  MUX_VAL(CP(MMC2_DAT7),         (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
 214  /*Bluetooth*/\
 215  MUX_VAL(CP(MCBSP3_DX),         (IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
 216  MUX_VAL(CP(MCBSP3_DR),         (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
 217  MUX_VAL(CP(MCBSP3_CLKX),       (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
 218  MUX_VAL(CP(MCBSP3_FSX),        (IEN  | PTD | DIS | M1)) /*UART2_RX*/\
 219  MUX_VAL(CP(UART2_CTS),         (IEN  | PTD | DIS | M4)) /*GPIO_144*/\
 220  MUX_VAL(CP(UART2_RTS),         (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
 221  MUX_VAL(CP(UART2_TX),          (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
 222  MUX_VAL(CP(UART2_RX),          (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
 223  /*Modem Interface */\
 224  MUX_VAL(CP(UART1_TX),          (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
 225  MUX_VAL(CP(UART1_RTS),         (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
 226  MUX_VAL(CP(UART1_CTS),         (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
 227  MUX_VAL(CP(UART1_RX),          (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
 228  MUX_VAL(CP(MCBSP4_CLKX),       (IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
 229  MUX_VAL(CP(MCBSP4_DR),         (IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
 230  MUX_VAL(CP(MCBSP4_DX),         (IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
 231  MUX_VAL(CP(MCBSP4_FSX),        (IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
 232  MUX_VAL(CP(MCBSP1_CLKR),       (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
 233  MUX_VAL(CP(MCBSP1_FSR),        (IDIS | PTU | EN  | M4)) /*GPIO_157*/\
 234  MUX_VAL(CP(MCBSP1_DX),         (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
 235  MUX_VAL(CP(MCBSP1_DR),         (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
 236  MUX_VAL(CP(MCBSP_CLKS),        (IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
 237  MUX_VAL(CP(MCBSP1_FSX),        (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
 238  MUX_VAL(CP(MCBSP1_CLKX),       (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
 239  /*Serial Interface*/\
 240  MUX_VAL(CP(UART3_CTS_RCTX),    (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
 241  MUX_VAL(CP(UART3_RTS_SD),      (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
 242  MUX_VAL(CP(UART3_RX_IRRX),     (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
 243  MUX_VAL(CP(UART3_TX_IRTX),     (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 244  MUX_VAL(CP(HSUSB0_CLK),        (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
 245  MUX_VAL(CP(HSUSB0_STP),        (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
 246  MUX_VAL(CP(HSUSB0_DIR),        (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
 247  MUX_VAL(CP(HSUSB0_NXT),        (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
 248  MUX_VAL(CP(HSUSB0_DATA0),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
 249  MUX_VAL(CP(HSUSB0_DATA1),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
 250  MUX_VAL(CP(HSUSB0_DATA2),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
 251  MUX_VAL(CP(HSUSB0_DATA3),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
 252  MUX_VAL(CP(HSUSB0_DATA4),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
 253  MUX_VAL(CP(HSUSB0_DATA5),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
 254  MUX_VAL(CP(HSUSB0_DATA6),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
 255  MUX_VAL(CP(HSUSB0_DATA7),      (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
 256  MUX_VAL(CP(I2C1_SCL),          (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
 257  MUX_VAL(CP(I2C1_SDA),          (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
 258  MUX_VAL(CP(I2C2_SCL),          (IEN  | PTU | EN  | M4)) /*GPIO_168*/\
 259  MUX_VAL(CP(I2C2_SDA),          (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
 260  MUX_VAL(CP(I2C3_SCL),          (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
 261  MUX_VAL(CP(I2C3_SDA),          (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
 262  MUX_VAL(CP(I2C4_SCL),          (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
 263  MUX_VAL(CP(I2C4_SDA),          (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
 264  MUX_VAL(CP(HDQ_SIO),           (IDIS | PTU | EN  | M4)) /*GPIO_170*/\
 265  MUX_VAL(CP(MCSPI1_CLK),        (IEN  | PTU | EN  | M4)) /*GPIO_171*/\
 266  MUX_VAL(CP(MCSPI1_SIMO),       (IEN  | PTU | EN  | M4)) /*GPIO_172*/\
 267  MUX_VAL(CP(MCSPI1_SOMI),       (IEN  | PTD | DIS | M0)) /*McSPI1_SOMI*/\
 268  MUX_VAL(CP(MCSPI1_CS0),        (IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
 269  MUX_VAL(CP(MCSPI1_CS1),        (IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
 270  MUX_VAL(CP(MCSPI1_CS2),        (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
 271  /* USB EHCI (port 2) */\
 272  MUX_VAL(CP(MCSPI1_CS3),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
 273  MUX_VAL(CP(MCSPI2_CLK),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
 274  MUX_VAL(CP(MCSPI2_SIMO),       (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
 275  MUX_VAL(CP(MCSPI2_SOMI),       (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
 276  MUX_VAL(CP(MCSPI2_CS0),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
 277  MUX_VAL(CP(MCSPI2_CS1),        (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
 278  MUX_VAL(CP(ETK_D10_ES2),       (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
 279  MUX_VAL(CP(ETK_D11_ES2),       (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
 280  MUX_VAL(CP(ETK_D12_ES2),       (IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
 281  MUX_VAL(CP(ETK_D13_ES2),       (IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
 282  MUX_VAL(CP(ETK_D14_ES2),       (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
 283  MUX_VAL(CP(ETK_D15_ES2),       (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
 284  /*Control and debug */\
 285  MUX_VAL(CP(SYS_32K),           (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 286  MUX_VAL(CP(SYS_CLKREQ),        (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
 287  MUX_VAL(CP(SYS_NIRQ),          (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
 288  MUX_VAL(CP(SYS_BOOT0),         (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 289  MUX_VAL(CP(SYS_BOOT1),         (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
 290  MUX_VAL(CP(SYS_BOOT2),         (IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
 291  MUX_VAL(CP(SYS_BOOT3),         (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
 292  MUX_VAL(CP(SYS_BOOT4),         (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
 293  MUX_VAL(CP(SYS_BOOT5),         (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
 294  MUX_VAL(CP(SYS_BOOT6),         (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
 295  MUX_VAL(CP(SYS_OFF_MODE),      (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 296  MUX_VAL(CP(SYS_CLKOUT1),       (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
 297  MUX_VAL(CP(SYS_CLKOUT2),       (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
 298  MUX_VAL(CP(ETK_CLK_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_STP*/\
 299  MUX_VAL(CP(ETK_CTL_ES2),       (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
 300  MUX_VAL(CP(ETK_D0_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
 301  MUX_VAL(CP(ETK_D1_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
 302  MUX_VAL(CP(ETK_D2_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
 303  MUX_VAL(CP(ETK_D3_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
 304  MUX_VAL(CP(ETK_D4_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
 305  MUX_VAL(CP(ETK_D5_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
 306  MUX_VAL(CP(ETK_D6_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
 307  MUX_VAL(CP(ETK_D7_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
 308  MUX_VAL(CP(ETK_D8_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
 309  MUX_VAL(CP(ETK_D9_ES2),        (IEN  | PTU | DIS | M3)) /*HSUSB1_NXT*/\
 310  MUX_VAL(CP(D2D_MCAD1),         (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
 311  MUX_VAL(CP(D2D_MCAD2),         (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
 312  MUX_VAL(CP(D2D_MCAD3),         (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
 313  MUX_VAL(CP(D2D_MCAD4),         (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
 314  MUX_VAL(CP(D2D_MCAD5),         (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
 315  MUX_VAL(CP(D2D_MCAD6),         (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
 316  MUX_VAL(CP(D2D_MCAD7),         (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
 317  MUX_VAL(CP(D2D_MCAD8),         (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
 318  MUX_VAL(CP(D2D_MCAD9),         (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
 319  MUX_VAL(CP(D2D_MCAD10),        (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
 320  MUX_VAL(CP(D2D_MCAD11),        (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
 321  MUX_VAL(CP(D2D_MCAD12),        (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
 322  MUX_VAL(CP(D2D_MCAD13),        (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
 323  MUX_VAL(CP(D2D_MCAD14),        (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
 324  MUX_VAL(CP(D2D_MCAD15),        (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
 325  MUX_VAL(CP(D2D_MCAD16),        (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
 326  MUX_VAL(CP(D2D_MCAD17),        (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
 327  MUX_VAL(CP(D2D_MCAD18),        (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
 328  MUX_VAL(CP(D2D_MCAD19),        (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
 329  MUX_VAL(CP(D2D_MCAD20),        (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
 330  MUX_VAL(CP(D2D_MCAD21),        (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
 331  MUX_VAL(CP(D2D_MCAD22),        (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
 332  MUX_VAL(CP(D2D_MCAD23),        (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
 333  MUX_VAL(CP(D2D_MCAD24),        (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
 334  MUX_VAL(CP(D2D_MCAD25),        (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
 335  MUX_VAL(CP(D2D_MCAD26),        (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
 336  MUX_VAL(CP(D2D_MCAD27),        (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
 337  MUX_VAL(CP(D2D_MCAD28),        (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
 338  MUX_VAL(CP(D2D_MCAD29),        (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
 339  MUX_VAL(CP(D2D_MCAD30),        (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
 340  MUX_VAL(CP(D2D_MCAD31),        (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
 341  MUX_VAL(CP(D2D_MCAD32),        (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
 342  MUX_VAL(CP(D2D_MCAD33),        (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
 343  MUX_VAL(CP(D2D_MCAD34),        (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
 344  MUX_VAL(CP(D2D_MCAD35),        (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
 345  MUX_VAL(CP(D2D_MCAD36),        (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
 346  MUX_VAL(CP(D2D_CLK26MI),       (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
 347  MUX_VAL(CP(D2D_NRESPWRON),     (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
 348  MUX_VAL(CP(D2D_NRESWARM),      (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
 349  MUX_VAL(CP(D2D_ARM9NIRQ),      (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
 350  MUX_VAL(CP(D2D_UMA2P6FIQ),     (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
 351  MUX_VAL(CP(D2D_SPINT),         (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
 352  MUX_VAL(CP(D2D_FRINT),         (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
 353  MUX_VAL(CP(D2D_DMAREQ0),       (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
 354  MUX_VAL(CP(D2D_DMAREQ1),       (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
 355  MUX_VAL(CP(D2D_DMAREQ2),       (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
 356  MUX_VAL(CP(D2D_DMAREQ3),       (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
 357  MUX_VAL(CP(D2D_N3GTRST),       (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
 358  MUX_VAL(CP(D2D_N3GTDI),        (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
 359  MUX_VAL(CP(D2D_N3GTDO),        (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
 360  MUX_VAL(CP(D2D_N3GTMS),        (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
 361  MUX_VAL(CP(D2D_N3GTCK),        (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
 362  MUX_VAL(CP(D2D_N3GRTCK),       (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
 363  MUX_VAL(CP(D2D_MSTDBY),        (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
 364  MUX_VAL(CP(D2D_SWAKEUP),       (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
 365  MUX_VAL(CP(D2D_IDLEREQ),       (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
 366  MUX_VAL(CP(D2D_IDLEACK),       (IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
 367  MUX_VAL(CP(D2D_MWRITE),        (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
 368  MUX_VAL(CP(D2D_SWRITE),        (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
 369  MUX_VAL(CP(D2D_MREAD),         (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
 370  MUX_VAL(CP(D2D_SREAD),         (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
 371  MUX_VAL(CP(D2D_MBUSFLAG),      (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
 372  MUX_VAL(CP(D2D_SBUSFLAG),      (IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
 373  MUX_VAL(CP(SDRC_CKE0),         (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
 374  MUX_VAL(CP(SDRC_CKE1),         (IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 375
 376 #define MUX_BEAGLE_C() \
 377  MUX_VAL(CP(MCBSP3_DX),         (IEN | PTD | DIS | M4)) /*GPIO_140*/\
 378  MUX_VAL(CP(MCBSP3_DR),         (IEN | PTD | DIS | M4)) /*GPIO_142*/\
 379  MUX_VAL(CP(MCBSP3_CLKX),       (IEN | PTD | DIS | M4)) /*GPIO_141*/\
 380  MUX_VAL(CP(UART2_CTS),         (IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
 381  MUX_VAL(CP(UART2_RTS),         (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
 382  MUX_VAL(CP(UART2_TX),          (IDIS | PTD | DIS | M0)) /*UART2_TX*/
 383
 384 #endif