3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/string.h>
19 #include <linux/usb/gadget.h>
20 #include <asm/omap_common.h>
21 #include <asm/omap_sec_common.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/dra7xx_iodelay.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/sata.h>
28 #include <environment.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
35 #include "../common/board_detect.h"
37 #define board_is_dra74x_evm() board_ti_is("5777xCPU")
38 #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
39 #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
40 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
41 (strncmp("H", board_ti_get_rev(), 1) <= 0))
42 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
43 (strncmp("C", board_ti_get_rev(), 1) <= 0))
44 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
45 board_ti_get_emif2_size()
47 #ifdef CONFIG_DRIVER_TI_CPSW
51 DECLARE_GLOBAL_DATA_PTR
;
54 #define GPIO_DDR_VTT_EN 203
56 #define SYSINFO_BOARD_NAME_MAX_LEN 37
58 const struct omap_sysinfo sysinfo
= {
59 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
62 static const struct emif_regs emif1_ddr3_532_mhz_1cs
= {
63 .sdram_config_init
= 0x61851ab2,
64 .sdram_config
= 0x61851ab2,
65 .sdram_config2
= 0x08000000,
66 .ref_ctrl
= 0x000040F1,
67 .ref_ctrl_final
= 0x00001035,
68 .sdram_tim1
= 0xCCCF36B3,
69 .sdram_tim2
= 0x308F7FDA,
70 .sdram_tim3
= 0x427F88A8,
71 .read_idle_ctrl
= 0x00050000,
72 .zq_config
= 0x0007190B,
73 .temp_alert_config
= 0x00000000,
74 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
75 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
76 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
77 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
78 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
79 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
80 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
81 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
82 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
83 .emif_rd_wr_lvl_ctl
= 0x00000000,
84 .emif_rd_wr_exec_thresh
= 0x00000305
87 static const struct emif_regs emif2_ddr3_532_mhz_1cs
= {
88 .sdram_config_init
= 0x61851B32,
89 .sdram_config
= 0x61851B32,
90 .sdram_config2
= 0x08000000,
91 .ref_ctrl
= 0x000040F1,
92 .ref_ctrl_final
= 0x00001035,
93 .sdram_tim1
= 0xCCCF36B3,
94 .sdram_tim2
= 0x308F7FDA,
95 .sdram_tim3
= 0x427F88A8,
96 .read_idle_ctrl
= 0x00050000,
97 .zq_config
= 0x0007190B,
98 .temp_alert_config
= 0x00000000,
99 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
100 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
101 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
102 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
103 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
104 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
105 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
106 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
107 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
108 .emif_rd_wr_lvl_ctl
= 0x00000000,
109 .emif_rd_wr_exec_thresh
= 0x00000305
112 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1
= {
113 .sdram_config_init
= 0x61862B32,
114 .sdram_config
= 0x61862B32,
115 .sdram_config2
= 0x08000000,
116 .ref_ctrl
= 0x0000514C,
117 .ref_ctrl_final
= 0x0000144A,
118 .sdram_tim1
= 0xD113781C,
119 .sdram_tim2
= 0x30717FE3,
120 .sdram_tim3
= 0x409F86A8,
121 .read_idle_ctrl
= 0x00050000,
122 .zq_config
= 0x5007190B,
123 .temp_alert_config
= 0x00000000,
124 .emif_ddr_phy_ctlr_1_init
= 0x0024400D,
125 .emif_ddr_phy_ctlr_1
= 0x0E24400D,
126 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
127 .emif_ddr_ext_phy_ctrl_2
= 0x00A400A4,
128 .emif_ddr_ext_phy_ctrl_3
= 0x00A900A9,
129 .emif_ddr_ext_phy_ctrl_4
= 0x00B000B0,
130 .emif_ddr_ext_phy_ctrl_5
= 0x00B000B0,
131 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
132 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
133 .emif_rd_wr_lvl_ctl
= 0x00000000,
134 .emif_rd_wr_exec_thresh
= 0x00000305
137 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2
= {
138 .sdram_config_init
= 0x61862BB2,
139 .sdram_config
= 0x61862BB2,
140 .sdram_config2
= 0x00000000,
141 .ref_ctrl
= 0x0000514D,
142 .ref_ctrl_final
= 0x0000144A,
143 .sdram_tim1
= 0xD1137824,
144 .sdram_tim2
= 0x30B37FE3,
145 .sdram_tim3
= 0x409F8AD8,
146 .read_idle_ctrl
= 0x00050000,
147 .zq_config
= 0x5007190B,
148 .temp_alert_config
= 0x00000000,
149 .emif_ddr_phy_ctlr_1_init
= 0x0824400E,
150 .emif_ddr_phy_ctlr_1
= 0x0E24400E,
151 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
152 .emif_ddr_ext_phy_ctrl_2
= 0x006B009F,
153 .emif_ddr_ext_phy_ctrl_3
= 0x006B00A2,
154 .emif_ddr_ext_phy_ctrl_4
= 0x006B00A8,
155 .emif_ddr_ext_phy_ctrl_5
= 0x006B00A8,
156 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
157 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
158 .emif_rd_wr_lvl_ctl
= 0x00000000,
159 .emif_rd_wr_exec_thresh
= 0x00000305
162 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G
= {
163 .sdram_config_init
= 0x61851ab2,
164 .sdram_config
= 0x61851ab2,
165 .sdram_config2
= 0x08000000,
166 .ref_ctrl
= 0x000040F1,
167 .ref_ctrl_final
= 0x00001035,
168 .sdram_tim1
= 0xCCCF36B3,
169 .sdram_tim2
= 0x30BF7FDA,
170 .sdram_tim3
= 0x427F8BA8,
171 .read_idle_ctrl
= 0x00050000,
172 .zq_config
= 0x0007190B,
173 .temp_alert_config
= 0x00000000,
174 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
175 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
176 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
177 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
178 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
179 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
180 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
181 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
182 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
183 .emif_rd_wr_lvl_ctl
= 0x00000000,
184 .emif_rd_wr_exec_thresh
= 0x00000305
187 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G
= {
188 .sdram_config_init
= 0x61851B32,
189 .sdram_config
= 0x61851B32,
190 .sdram_config2
= 0x08000000,
191 .ref_ctrl
= 0x000040F1,
192 .ref_ctrl_final
= 0x00001035,
193 .sdram_tim1
= 0xCCCF36B3,
194 .sdram_tim2
= 0x308F7FDA,
195 .sdram_tim3
= 0x427F88A8,
196 .read_idle_ctrl
= 0x00050000,
197 .zq_config
= 0x0007190B,
198 .temp_alert_config
= 0x00000000,
199 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
200 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
201 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
202 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
203 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
204 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
205 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
206 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
207 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
208 .emif_rd_wr_lvl_ctl
= 0x00000000,
209 .emif_rd_wr_exec_thresh
= 0x00000305
212 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
216 ram_size
= board_ti_get_emif_size();
218 switch (omap_revision()) {
224 if (ram_size
> CONFIG_MAX_MEM_MAPPED
)
225 *regs
= &emif1_ddr3_532_mhz_1cs_2G
;
227 *regs
= &emif1_ddr3_532_mhz_1cs
;
230 if (ram_size
> CONFIG_MAX_MEM_MAPPED
)
231 *regs
= &emif2_ddr3_532_mhz_1cs_2G
;
233 *regs
= &emif2_ddr3_532_mhz_1cs
;
239 if (ram_size
< CONFIG_MAX_MEM_MAPPED
)
240 *regs
= &emif_1_regs_ddr3_666_mhz_1cs_dra_es1
;
242 *regs
= &emif_1_regs_ddr3_666_mhz_1cs_dra_es2
;
245 *regs
= &emif1_ddr3_532_mhz_1cs
;
249 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB
= {
250 .dmm_lisa_map_0
= 0x0,
251 .dmm_lisa_map_1
= 0x80640300,
252 .dmm_lisa_map_2
= 0xC0500220,
253 .dmm_lisa_map_3
= 0xFF020100,
257 static const struct dmm_lisa_map_regs lisa_map_2G_x_2
= {
258 .dmm_lisa_map_0
= 0x0,
259 .dmm_lisa_map_1
= 0x0,
260 .dmm_lisa_map_2
= 0x80600100,
261 .dmm_lisa_map_3
= 0xFF020100,
265 const struct dmm_lisa_map_regs lisa_map_dra7_2GB
= {
266 .dmm_lisa_map_0
= 0x0,
267 .dmm_lisa_map_1
= 0x0,
268 .dmm_lisa_map_2
= 0x80740300,
269 .dmm_lisa_map_3
= 0xFF020100,
274 * DRA722 EVM EMIF1 2GB CONFIGURATION
275 * EMIF1 4 devices of 512Mb x 8 Micron
277 const struct dmm_lisa_map_regs lisa_map_2G_x_4
= {
278 .dmm_lisa_map_0
= 0x0,
279 .dmm_lisa_map_1
= 0x0,
280 .dmm_lisa_map_2
= 0x80700100,
281 .dmm_lisa_map_3
= 0xFF020100,
285 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
289 ram_size
= board_ti_get_emif_size();
291 switch (omap_revision()) {
295 if (ram_size
> CONFIG_MAX_MEM_MAPPED
)
296 *dmm_lisa_regs
= &lisa_map_dra7_2GB
;
298 *dmm_lisa_regs
= &lisa_map_dra7_1536MB
;
303 if (ram_size
< CONFIG_MAX_MEM_MAPPED
)
304 *dmm_lisa_regs
= &lisa_map_2G_x_2
;
306 *dmm_lisa_regs
= &lisa_map_2G_x_4
;
311 struct vcores_data dra752_volts
= {
312 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
313 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
314 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
315 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
316 .mpu
.pmic
= &tps659038
,
317 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
319 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
320 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
321 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
322 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
323 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
324 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
325 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
326 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
327 .eve
.pmic
= &tps659038
,
328 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
330 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
331 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
332 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
333 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
334 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
335 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
336 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
337 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
338 .gpu
.pmic
= &tps659038
,
339 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
341 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
342 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
343 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
344 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
345 .core
.pmic
= &tps659038
,
347 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
348 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
349 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
350 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
351 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
352 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
353 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
354 .iva
.addr
= TPS659038_REG_ADDR_SMPS8
,
355 .iva
.pmic
= &tps659038
,
356 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
359 struct vcores_data dra722_volts
= {
360 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
361 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
362 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
363 .mpu
.addr
= TPS65917_REG_ADDR_SMPS1
,
364 .mpu
.pmic
= &tps659038
,
365 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
367 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
368 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
369 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
370 .core
.addr
= TPS65917_REG_ADDR_SMPS2
,
371 .core
.pmic
= &tps659038
,
374 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
375 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
377 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
378 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
379 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
380 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
381 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
382 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
383 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
384 .gpu
.addr
= TPS65917_REG_ADDR_SMPS3
,
385 .gpu
.pmic
= &tps659038
,
386 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
388 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
389 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
390 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
391 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
392 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
393 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
394 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
395 .eve
.addr
= TPS65917_REG_ADDR_SMPS3
,
396 .eve
.pmic
= &tps659038
,
397 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
399 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
400 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
401 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
402 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
403 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
404 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
405 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
406 .iva
.addr
= TPS65917_REG_ADDR_SMPS3
,
407 .iva
.pmic
= &tps659038
,
408 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
411 struct vcores_data dra718_volts
= {
413 * In the case of dra71x GPU MPU and CORE
414 * are all powered up by BUCK0 of LP873X PMIC
416 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
417 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
418 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
419 .mpu
.addr
= LP873X_REG_ADDR_BUCK0
,
421 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
423 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
424 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
425 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
426 .core
.addr
= LP873X_REG_ADDR_BUCK0
,
427 .core
.pmic
= &lp8733
,
429 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
430 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
431 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
432 .gpu
.addr
= LP873X_REG_ADDR_BUCK0
,
434 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
437 * The DSPEVE and IVA rails are grouped on DRA71x-evm
438 * and are powered by BUCK1 of LP873X PMIC
440 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
441 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
442 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
443 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
444 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
445 .eve
.addr
= LP873X_REG_ADDR_BUCK1
,
447 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
449 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
450 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
451 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
452 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
453 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
454 .iva
.addr
= LP873X_REG_ADDR_BUCK1
,
456 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
459 int get_voltrail_opp(int rail_offset
)
463 switch (rail_offset
) {
466 /* DRA71x supports only OPP_NOM for MPU */
467 if (board_is_dra71x_evm())
472 /* DRA71x supports only OPP_NOM for CORE */
473 if (board_is_dra71x_evm())
478 /* DRA71x supports only OPP_NOM for GPU */
479 if (board_is_dra71x_evm())
483 opp
= DRA7_DSPEVE_OPP
;
485 * DRA71x does not support OPP_OD for EVE.
486 * If OPP_OD is selected by menuconfig, fallback
489 if (board_is_dra71x_evm() && opp
== OPP_OD
)
495 * DRA71x does not support OPP_OD for IVA.
496 * If OPP_OD is selected by menuconfig, fallback
499 if (board_is_dra71x_evm() && opp
== OPP_OD
)
517 gd
->bd
->bi_boot_params
= (0x80000000 + 0x100); /* boot param addr */
522 int dram_init_banksize(void)
526 ram_size
= board_ti_get_emif_size();
528 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
529 gd
->bd
->bi_dram
[0].size
= get_effective_memsize();
530 if (ram_size
> CONFIG_MAX_MEM_MAPPED
) {
531 gd
->bd
->bi_dram
[1].start
= 0x200000000;
532 gd
->bd
->bi_dram
[1].size
= ram_size
- CONFIG_MAX_MEM_MAPPED
;
538 int board_late_init(void)
540 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
541 char *name
= "unknown";
544 if (board_is_dra72x_revc_or_later())
545 name
= "dra72x-revc";
546 else if (board_is_dra71x_evm())
554 set_board_info_env(name
);
557 * Default FIT boot on HS devices. Non FIT images are not allowed
560 if (get_device_type() == HS_DEVICE
)
561 env_set("boot_fit", "1");
563 omap_die_id_serial();
564 omap_set_fastboot_vars();
569 #ifdef CONFIG_SPL_BUILD
570 void do_board_detect(void)
574 rc
= ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS
,
575 CONFIG_EEPROM_CHIP_ADDRESS
);
577 printf("ti_i2c_eeprom_init failed %d\n", rc
);
582 void do_board_detect(void)
587 rc
= ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS
,
588 CONFIG_EEPROM_CHIP_ADDRESS
);
590 printf("ti_i2c_eeprom_init failed %d\n", rc
);
592 if (board_is_dra74x_evm()) {
593 bname
= "DRA74x EVM";
594 } else if (board_is_dra72x_evm()) {
595 bname
= "DRA72x EVM";
596 } else if (board_is_dra71x_evm()) {
597 bname
= "DRA71x EVM";
599 /* If EEPROM is not populated */
601 bname
= "DRA72x EVM";
603 bname
= "DRA74x EVM";
607 snprintf(sysinfo
.board_string
, SYSINFO_BOARD_NAME_MAX_LEN
,
608 "Board: %s REV %s\n", bname
, board_ti_get_rev());
610 #endif /* CONFIG_SPL_BUILD */
612 void vcores_init(void)
614 if (board_is_dra74x_evm()) {
615 *omap_vcores
= &dra752_volts
;
616 } else if (board_is_dra72x_evm()) {
617 *omap_vcores
= &dra722_volts
;
618 } else if (board_is_dra71x_evm()) {
619 *omap_vcores
= &dra718_volts
;
621 /* If EEPROM is not populated */
623 *omap_vcores
= &dra722_volts
;
625 *omap_vcores
= &dra752_volts
;
629 void set_muxconf_regs(void)
631 do_set_mux32((*ctrl
)->control_padconf_core_base
,
632 early_padconf
, ARRAY_SIZE(early_padconf
));
635 #ifdef CONFIG_IODELAY_RECALIBRATION
636 void recalibrate_iodelay(void)
638 struct pad_conf_entry
const *pads
, *delta_pads
= NULL
;
639 struct iodelay_cfg_entry
const *iodelay
;
640 int npads
, niodelays
, delta_npads
= 0;
643 switch (omap_revision()) {
646 pads
= dra72x_core_padconf_array_common
;
647 npads
= ARRAY_SIZE(dra72x_core_padconf_array_common
);
648 if (board_is_dra71x_evm()) {
649 pads
= dra71x_core_padconf_array
;
650 npads
= ARRAY_SIZE(dra71x_core_padconf_array
);
651 iodelay
= dra71_iodelay_cfg_array
;
652 niodelays
= ARRAY_SIZE(dra71_iodelay_cfg_array
);
653 } else if (board_is_dra72x_revc_or_later()) {
654 delta_pads
= dra72x_rgmii_padconf_array_revc
;
656 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc
);
657 iodelay
= dra72_iodelay_cfg_array_revc
;
658 niodelays
= ARRAY_SIZE(dra72_iodelay_cfg_array_revc
);
660 delta_pads
= dra72x_rgmii_padconf_array_revb
;
662 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb
);
663 iodelay
= dra72_iodelay_cfg_array_revb
;
664 niodelays
= ARRAY_SIZE(dra72_iodelay_cfg_array_revb
);
669 pads
= dra74x_core_padconf_array
;
670 npads
= ARRAY_SIZE(dra74x_core_padconf_array
);
671 iodelay
= dra742_es1_1_iodelay_cfg_array
;
672 niodelays
= ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array
);
676 pads
= dra74x_core_padconf_array
;
677 npads
= ARRAY_SIZE(dra74x_core_padconf_array
);
678 iodelay
= dra742_es2_0_iodelay_cfg_array
;
679 niodelays
= ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array
);
680 /* Setup port1 and port2 for rgmii with 'no-id' mode */
681 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK
|
682 RGMII1_ID_MODE_N_MASK
);
685 /* Setup I/O isolation */
686 ret
= __recalibrate_iodelay_start();
690 /* Do the muxing here */
691 do_set_mux32((*ctrl
)->control_padconf_core_base
, pads
, npads
);
693 /* Now do the weird minor deltas that should be safe */
695 do_set_mux32((*ctrl
)->control_padconf_core_base
,
696 delta_pads
, delta_npads
);
698 /* Setup IOdelay configuration */
699 ret
= do_set_iodelay((*ctrl
)->iodelay_config_base
, iodelay
, niodelays
);
701 /* Closeup.. remove isolation */
702 __recalibrate_iodelay_end(ret
);
706 #if defined(CONFIG_MMC)
707 int board_mmc_init(bd_t
*bis
)
709 omap_mmc_init(0, 0, 0, -1, -1);
710 omap_mmc_init(1, 0, 0, -1, -1);
715 #ifdef CONFIG_USB_DWC3
716 static struct dwc3_device usb_otg_ss1
= {
717 .maximum_speed
= USB_SPEED_SUPER
,
718 .base
= DRA7_USB_OTG_SS1_BASE
,
719 .tx_fifo_resize
= false,
723 static struct dwc3_omap_device usb_otg_ss1_glue
= {
724 .base
= (void *)DRA7_USB_OTG_SS1_GLUE_BASE
,
725 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
729 static struct ti_usb_phy_device usb_phy1_device
= {
730 .pll_ctrl_base
= (void *)DRA7_USB3_PHY1_PLL_CTRL
,
731 .usb2_phy_power
= (void *)DRA7_USB2_PHY1_POWER
,
732 .usb3_phy_power
= (void *)DRA7_USB3_PHY1_POWER
,
736 static struct dwc3_device usb_otg_ss2
= {
737 .maximum_speed
= USB_SPEED_SUPER
,
738 .base
= DRA7_USB_OTG_SS2_BASE
,
739 .tx_fifo_resize
= false,
743 static struct dwc3_omap_device usb_otg_ss2_glue
= {
744 .base
= (void *)DRA7_USB_OTG_SS2_GLUE_BASE
,
745 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
749 static struct ti_usb_phy_device usb_phy2_device
= {
750 .usb2_phy_power
= (void *)DRA7_USB2_PHY2_POWER
,
754 int omap_xhci_board_usb_init(int index
, enum usb_init_type init
)
756 enable_usb_clocks(index
);
759 if (init
== USB_INIT_DEVICE
) {
760 usb_otg_ss1
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
761 usb_otg_ss1_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
763 usb_otg_ss1
.dr_mode
= USB_DR_MODE_HOST
;
764 usb_otg_ss1_glue
.vbus_id_status
= OMAP_DWC3_ID_GROUND
;
767 ti_usb_phy_uboot_init(&usb_phy1_device
);
768 dwc3_omap_uboot_init(&usb_otg_ss1_glue
);
769 dwc3_uboot_init(&usb_otg_ss1
);
772 if (init
== USB_INIT_DEVICE
) {
773 usb_otg_ss2
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
774 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
776 usb_otg_ss2
.dr_mode
= USB_DR_MODE_HOST
;
777 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_ID_GROUND
;
780 ti_usb_phy_uboot_init(&usb_phy2_device
);
781 dwc3_omap_uboot_init(&usb_otg_ss2_glue
);
782 dwc3_uboot_init(&usb_otg_ss2
);
785 printf("Invalid Controller Index\n");
791 int omap_xhci_board_usb_cleanup(int index
, enum usb_init_type init
)
796 ti_usb_phy_uboot_exit(index
);
797 dwc3_uboot_exit(index
);
798 dwc3_omap_uboot_exit(index
);
801 printf("Invalid Controller Index\n");
803 disable_usb_clocks(index
);
807 int usb_gadget_handle_interrupts(int index
)
811 status
= dwc3_omap_uboot_interrupt_status(index
);
813 dwc3_uboot_handle_interrupt(index
);
819 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
820 int spl_start_uboot(void)
822 /* break into full u-boot on 'c' */
823 if (serial_tstc() && serial_getc() == 'c')
826 #ifdef CONFIG_SPL_ENV_SUPPORT
829 if (getenv_yesno("boot_os") != 1)
837 #ifdef CONFIG_DRIVER_TI_CPSW
838 extern u32
*const omap_si_rev
;
840 static void cpsw_control(int enabled
)
842 /* VTP can be added here */
847 static struct cpsw_slave_data cpsw_slaves
[] = {
849 .slave_reg_ofs
= 0x208,
850 .sliver_reg_ofs
= 0xd80,
854 .slave_reg_ofs
= 0x308,
855 .sliver_reg_ofs
= 0xdc0,
860 static struct cpsw_platform_data cpsw_data
= {
861 .mdio_base
= CPSW_MDIO_BASE
,
862 .cpsw_base
= CPSW_BASE
,
865 .cpdma_reg_ofs
= 0x800,
867 .slave_data
= cpsw_slaves
,
868 .ale_reg_ofs
= 0xd00,
870 .host_port_reg_ofs
= 0x108,
871 .hw_stats_reg_ofs
= 0x900,
872 .bd_ram_ofs
= 0x2000,
873 .mac_control
= (1 << 5),
874 .control
= cpsw_control
,
876 .version
= CPSW_CTRL_VERSION_2
,
879 int board_eth_init(bd_t
*bis
)
883 uint32_t mac_hi
, mac_lo
;
886 /* try reading mac address from efuse */
887 mac_lo
= readl((*ctrl
)->control_core_mac_id_0_lo
);
888 mac_hi
= readl((*ctrl
)->control_core_mac_id_0_hi
);
889 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
890 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
891 mac_addr
[2] = mac_hi
& 0xFF;
892 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
893 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
894 mac_addr
[5] = mac_lo
& 0xFF;
896 if (!getenv("ethaddr")) {
897 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
899 if (is_valid_ethaddr(mac_addr
))
900 eth_env_set_enetaddr("ethaddr", mac_addr
);
903 mac_lo
= readl((*ctrl
)->control_core_mac_id_1_lo
);
904 mac_hi
= readl((*ctrl
)->control_core_mac_id_1_hi
);
905 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
906 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
907 mac_addr
[2] = mac_hi
& 0xFF;
908 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
909 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
910 mac_addr
[5] = mac_lo
& 0xFF;
912 if (!getenv("eth1addr")) {
913 if (is_valid_ethaddr(mac_addr
))
914 eth_env_set_enetaddr("eth1addr", mac_addr
);
917 ctrl_val
= readl((*ctrl
)->control_core_control_io1
) & (~0x33);
919 writel(ctrl_val
, (*ctrl
)->control_core_control_io1
);
921 if (*omap_si_rev
== DRA722_ES1_0
)
922 cpsw_data
.active_slave
= 1;
924 if (board_is_dra72x_revc_or_later()) {
925 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII_ID
;
926 cpsw_slaves
[1].phy_if
= PHY_INTERFACE_MODE_RGMII_ID
;
929 ret
= cpsw_register(&cpsw_data
);
931 printf("Error %d registering CPSW switch\n", ret
);
937 #ifdef CONFIG_BOARD_EARLY_INIT_F
938 /* VTT regulator enable */
939 static inline void vtt_regulator_enable(void)
941 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL
)
944 /* Do not enable VTT for DRA722 */
949 * EVM Rev G and later use gpio7_11 for DDR3 termination.
950 * This is safe enough to do on older revs.
952 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
953 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
956 int board_early_init_f(void)
958 vtt_regulator_enable();
963 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
964 int ft_board_setup(void *blob
, bd_t
*bd
)
966 ft_cpu_setup(blob
, bd
);
972 #ifdef CONFIG_SPL_LOAD_FIT
973 int board_fit_config_name_match(const char *name
)
976 if (board_is_dra71x_evm()) {
977 if (!strcmp(name
, "dra71-evm"))
979 }else if(board_is_dra72x_revc_or_later()) {
980 if (!strcmp(name
, "dra72-evm-revc"))
982 } else if (!strcmp(name
, "dra72-evm")) {
985 } else if (!is_dra72x() && !strcmp(name
, "dra7-evm")) {
993 #ifdef CONFIG_TI_SECURE_DEVICE
994 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
996 secure_boot_verify_image(p_image
, p_size
);
999 void board_tee_image_process(ulong tee_image
, size_t tee_size
)
1001 secure_tee_install((u32
)tee_image
);
1004 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE
, board_tee_image_process
);