board/ti/k2hk_evm/board.c

   1 /*
   2  * K2HK EVM : Board initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <exports.h>
  12 #include <fdt_support.h>
  13 #include <libfdt.h>
  14
  15 #include <asm/arch/ddr3.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/io.h>
  19 #include <asm/mach-types.h>
  20 #include <asm/arch/emac_defs.h>
  21 #include <asm/arch/psc_defs.h>
  22 #include <asm/ti-common/ti-aemif.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 u32 device_big_endian;
  27
  28 unsigned int external_clk[ext_clk_count] = {
  29         [sys_clk]       =       122880000,
  30         [alt_core_clk]  =       125000000,
  31         [pa_clk]        =       122880000,
  32         [tetris_clk]    =       125000000,
  33         [ddr3a_clk]     =       100000000,
  34         [ddr3b_clk]     =       100000000,
  35         [mcm_clk]       =       312500000,
  36         [pcie_clk]      =       100000000,
  37         [sgmii_srio_clk] =      156250000,
  38         [xgmii_clk]     =       156250000,
  39         [usb_clk]       =       100000000,
  40         [rp1_clk]       =       123456789    /* TODO: cannot find
  41                                                 what is that */
  42 };
  43
  44 static struct aemif_config aemif_configs[] = {
  45         {                       /* CS0 */
  46                 .mode           = AEMIF_MODE_NAND,
  47                 .wr_setup       = 0xf,
  48                 .wr_strobe      = 0x3f,
  49                 .wr_hold        = 7,
  50                 .rd_setup       = 0xf,
  51                 .rd_strobe      = 0x3f,
  52                 .rd_hold        = 7,
  53                 .turn_around    = 3,
  54                 .width          = AEMIF_WIDTH_8,
  55         },
  56
  57 };
  58
  59 static struct pll_init_data pll_config[] = {
  60         CORE_PLL_1228,
  61         PASS_PLL_983,
  62         TETRIS_PLL_1200,
  63 };
  64
  65 int dram_init(void)
  66 {
  67         ddr3_init();
  68
  69         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  70                                     CONFIG_MAX_RAM_BANK_SIZE);
  71         aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  72         return 0;
  73 }
  74
  75 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  76 struct eth_priv_t eth_priv_cfg[] = {
  77         {
  78                 .int_name       = "K2HK_EMAC",
  79                 .rx_flow        = 22,
  80                 .phy_addr       = 0,
  81                 .slave_port     = 1,
  82                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  83         },
  84         {
  85                 .int_name       = "K2HK_EMAC1",
  86                 .rx_flow        = 23,
  87                 .phy_addr       = 1,
  88                 .slave_port     = 2,
  89                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
  90         },
  91         {
  92                 .int_name       = "K2HK_EMAC2",
  93                 .rx_flow        = 24,
  94                 .phy_addr       = 2,
  95                 .slave_port     = 3,
  96                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
  97         },
  98         {
  99                 .int_name       = "K2HK_EMAC3",
 100                 .rx_flow        = 25,
 101                 .phy_addr       = 3,
 102                 .slave_port     = 4,
 103                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 104         },
 105 };
 106
 107 int get_eth_env_param(char *env_name)
 108 {
 109         char *env;
 110         int  res = -1;
 111
 112         env = getenv(env_name);
 113         if (env)
 114                 res = simple_strtol(env, NULL, 0);
 115
 116         return res;
 117 }
 118
 119 int board_eth_init(bd_t *bis)
 120 {
 121         int     j;
 122         int     res;
 123         char    link_type_name[32];
 124
 125         for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
 126              j++) {
 127                 sprintf(link_type_name, "sgmii%d_link_type", j);
 128                 res = get_eth_env_param(link_type_name);
 129                 if (res >= 0)
 130                         eth_priv_cfg[j].sgmii_link_type = res;
 131
 132                 keystone2_emac_initialize(&eth_priv_cfg[j]);
 133         }
 134
 135         return 0;
 136 }
 137 #endif
 138
 139 /* Byte swap the 32-bit data if the device is BE */
 140 int cpu_to_bus(u32 *ptr, u32 length)
 141 {
 142         u32 i;
 143
 144         if (device_big_endian)
 145                 for (i = 0; i < length; i++, ptr++)
 146                         *ptr = __swab32(*ptr);
 147
 148         return 0;
 149 }
 150
 151 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 152 int board_early_init_f(void)
 153 {
 154         init_plls(ARRAY_SIZE(pll_config), pll_config);
 155         return 0;
 156 }
 157 #endif
 158
 159 int board_init(void)
 160 {
 161         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 162
 163         return 0;
 164 }
 165
 166 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 167 #define K2_DDR3_START_ADDR 0x80000000
 168 void ft_board_setup(void *blob, bd_t *bd)
 169 {
 170         u64 start[2];
 171         u64 size[2];
 172         char name[32], *env, *endp;
 173         int lpae, nodeoffset;
 174         u32 ddr3a_size;
 175         int nbanks;
 176
 177         env = getenv("mem_lpae");
 178         lpae = env && simple_strtol(env, NULL, 0);
 179
 180         ddr3a_size = 0;
 181         if (lpae) {
 182                 env = getenv("ddr3a_size");
 183                 if (env)
 184                         ddr3a_size = simple_strtol(env, NULL, 10);
 185                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 186                         ddr3a_size = 0;
 187         }
 188
 189         nbanks = 1;
 190         start[0] = bd->bi_dram[0].start;
 191         size[0]  = bd->bi_dram[0].size;
 192
 193         /* adjust memory start address for LPAE */
 194         if (lpae) {
 195                 start[0] -= K2_DDR3_START_ADDR;
 196                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 197         }
 198
 199         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 200                 size[1] = ((u64)ddr3a_size - 2) << 30;
 201                 start[1] = 0x880000000;
 202                 nbanks++;
 203         }
 204
 205         /* reserve memory at start of bank */
 206         sprintf(name, "mem_reserve_head");
 207         env = getenv(name);
 208         if (env) {
 209                 start[0] += ustrtoul(env, &endp, 0);
 210                 size[0] -= ustrtoul(env, &endp, 0);
 211         }
 212
 213         sprintf(name, "mem_reserve");
 214         env = getenv(name);
 215         if (env)
 216                 size[0] -= ustrtoul(env, &endp, 0);
 217
 218         fdt_fixup_memory_banks(blob, start, size, nbanks);
 219
 220         /* Fix up the initrd */
 221         if (lpae) {
 222                 u64 initrd_start, initrd_end;
 223                 u32 *prop1, *prop2;
 224                 int err;
 225                 nodeoffset = fdt_path_offset(blob, "/chosen");
 226                 if (nodeoffset >= 0) {
 227                         prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
 228                                             "linux,initrd-start", NULL);
 229                         prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
 230                                             "linux,initrd-end", NULL);
 231                         if (prop1 && prop2) {
 232                                 initrd_start = __be32_to_cpu(*prop1);
 233                                 initrd_start -= K2_DDR3_START_ADDR;
 234                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 235                                 initrd_start = __cpu_to_be64(initrd_start);
 236                                 initrd_end = __be32_to_cpu(*prop2);
 237                                 initrd_end -= K2_DDR3_START_ADDR;
 238                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 239                                 initrd_end = __cpu_to_be64(initrd_end);
 240
 241                                 err = fdt_delprop(blob, nodeoffset,
 242                                                   "linux,initrd-start");
 243                                 if (err < 0)
 244                                         puts("error deleting initrd-start\n");
 245
 246                                 err = fdt_delprop(blob, nodeoffset,
 247                                                   "linux,initrd-end");
 248                                 if (err < 0)
 249                                         puts("error deleting initrd-end\n");
 250
 251                                 err = fdt_setprop(blob, nodeoffset,
 252                                                   "linux,initrd-start",
 253                                                   &initrd_start,
 254                                                   sizeof(initrd_start));
 255                                 if (err < 0)
 256                                         puts("error adding initrd-start\n");
 257
 258                                 err = fdt_setprop(blob, nodeoffset,
 259                                                   "linux,initrd-end",
 260                                                   &initrd_end,
 261                                                   sizeof(initrd_end));
 262                                 if (err < 0)
 263                                         puts("error adding linux,initrd-end\n");
 264                         }
 265                 }
 266         }
 267 }
 268
 269 void ft_board_setup_ex(void *blob, bd_t *bd)
 270 {
 271         int     lpae;
 272         char    *env;
 273         u64     *reserve_start, size;
 274
 275         env = getenv("mem_lpae");
 276         lpae = env && simple_strtol(env, NULL, 0);
 277
 278         if (lpae) {
 279                 /*
 280                  * the initrd and other reserved memory areas are
 281                  * embedded in in the DTB itslef. fix up these addresses
 282                  * to 36 bit format
 283                  */
 284                 reserve_start = (u64 *)((char *)blob +
 285                                        fdt_off_mem_rsvmap(blob));
 286                 while (1) {
 287                         *reserve_start = __cpu_to_be64(*reserve_start);
 288                         size = __cpu_to_be64(*(reserve_start + 1));
 289                         if (size) {
 290                                 *reserve_start -= K2_DDR3_START_ADDR;
 291                                 *reserve_start +=
 292                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 293                                 *reserve_start =
 294                                         __cpu_to_be64(*reserve_start);
 295                         } else {
 296                                 break;
 297                         }
 298                         reserve_start += 2;
 299                 }
 300         }
 301 }
 302 #endif