board/ti/ks2_evm/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone : Board initialization
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include "board.h"
  11 #include <env.h>
  12 #include <hang.h>
  13 #include <image.h>
  14 #include <init.h>
  15 #include <spl.h>
  16 #include <exports.h>
  17 #include <fdt_support.h>
  18 #include <asm/arch/ddr3.h>
  19 #include <asm/arch/psc_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/ti-common/ti-aemif.h>
  22 #include <asm/ti-common/keystone_net.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #if defined(CONFIG_TI_AEMIF)
  27 static struct aemif_config aemif_configs[] = {
  28         {                       /* CS0 */
  29                 .mode           = AEMIF_MODE_NAND,
  30                 .wr_setup       = 0xf,
  31                 .wr_strobe      = 0x3f,
  32                 .wr_hold        = 7,
  33                 .rd_setup       = 0xf,
  34                 .rd_strobe      = 0x3f,
  35                 .rd_hold        = 7,
  36                 .turn_around    = 3,
  37                 .width          = AEMIF_WIDTH_8,
  38         },
  39 };
  40 #endif
  41
  42 int dram_init(void)
  43 {
  44         u32 ddr3_size;
  45
  46         ddr3_size = ddr3_init();
  47
  48         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  49                                     CONFIG_MAX_RAM_BANK_SIZE);
  50 #if defined(CONFIG_TI_AEMIF)
  51         if (!board_is_k2g_ice())
  52                 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  53 #endif
  54
  55         if (!board_is_k2g_ice()) {
  56                 if (ddr3_size)
  57                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  58                 else
  59                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
  60                                       gd->ram_size >> 30);
  61         }
  62
  63         return 0;
  64 }
  65
  66 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
  67 {
  68         return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
  69 }
  70
  71 int board_init(void)
  72 {
  73         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  74         return 0;
  75 }
  76
  77 #ifdef CONFIG_SPL_BUILD
  78 void spl_board_init(void)
  79 {
  80         spl_init_keystone_plls();
  81         preloader_console_init();
  82 }
  83
  84 u32 spl_boot_device(void)
  85 {
  86 #if defined(CONFIG_SPL_SPI_LOAD)
  87         return BOOT_DEVICE_SPI;
  88 #else
  89         puts("Unknown boot device\n");
  90         hang();
  91 #endif
  92 }
  93 #endif
  94
  95 #ifdef CONFIG_OF_BOARD_SETUP
  96 int ft_board_setup(void *blob, bd_t *bd)
  97 {
  98         int lpae;
  99         char *env;
 100         char *endp;
 101         int nbanks;
 102         u64 size[2];
 103         u64 start[2];
 104         u32 ddr3a_size;
 105
 106         env = env_get("mem_lpae");
 107         lpae = env && simple_strtol(env, NULL, 0);
 108
 109         ddr3a_size = 0;
 110         if (lpae) {
 111                 ddr3a_size = ddr3_get_size();
 112                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 113                         ddr3a_size = 0;
 114         }
 115
 116         nbanks = 1;
 117         start[0] = bd->bi_dram[0].start;
 118         size[0]  = bd->bi_dram[0].size;
 119
 120         /* adjust memory start address for LPAE */
 121         if (lpae) {
 122                 start[0] -= CONFIG_SYS_SDRAM_BASE;
 123                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 124         }
 125
 126         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 127                 size[1] = ((u64)ddr3a_size - 2) << 30;
 128                 start[1] = 0x880000000;
 129                 nbanks++;
 130         }
 131
 132         /* reserve memory at start of bank */
 133         env = env_get("mem_reserve_head");
 134         if (env) {
 135                 start[0] += ustrtoul(env, &endp, 0);
 136                 size[0] -= ustrtoul(env, &endp, 0);
 137         }
 138
 139         env = env_get("mem_reserve");
 140         if (env)
 141                 size[0] -= ustrtoul(env, &endp, 0);
 142
 143         fdt_fixup_memory_banks(blob, start, size, nbanks);
 144
 145         return 0;
 146 }
 147
 148 void ft_board_setup_ex(void *blob, bd_t *bd)
 149 {
 150         int lpae;
 151         u64 size;
 152         char *env;
 153         u64 *reserve_start;
 154         int unitrd_fixup = 0;
 155
 156         env = env_get("mem_lpae");
 157         lpae = env && simple_strtol(env, NULL, 0);
 158         env = env_get("uinitrd_fixup");
 159         unitrd_fixup = env && simple_strtol(env, NULL, 0);
 160
 161         /* Fix up the initrd */
 162         if (lpae && unitrd_fixup) {
 163                 int nodeoffset;
 164                 int err;
 165                 u64 *prop1, *prop2;
 166                 u64 initrd_start, initrd_end;
 167
 168                 nodeoffset = fdt_path_offset(blob, "/chosen");
 169                 if (nodeoffset >= 0) {
 170                         prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
 171                                             "linux,initrd-start", NULL);
 172                         prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
 173                                             "linux,initrd-end", NULL);
 174                         if (prop1 && prop2) {
 175                                 initrd_start = __be64_to_cpu(*prop1);
 176                                 initrd_start -= CONFIG_SYS_SDRAM_BASE;
 177                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 178                                 initrd_start = __cpu_to_be64(initrd_start);
 179                                 initrd_end = __be64_to_cpu(*prop2);
 180                                 initrd_end -= CONFIG_SYS_SDRAM_BASE;
 181                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 182                                 initrd_end = __cpu_to_be64(initrd_end);
 183
 184                                 err = fdt_delprop(blob, nodeoffset,
 185                                                   "linux,initrd-start");
 186                                 if (err < 0)
 187                                         puts("error deleting initrd-start\n");
 188
 189                                 err = fdt_delprop(blob, nodeoffset,
 190                                                   "linux,initrd-end");
 191                                 if (err < 0)
 192                                         puts("error deleting initrd-end\n");
 193
 194                                 err = fdt_setprop(blob, nodeoffset,
 195                                                   "linux,initrd-start",
 196                                                   &initrd_start,
 197                                                   sizeof(initrd_start));
 198                                 if (err < 0)
 199                                         puts("error adding initrd-start\n");
 200
 201                                 err = fdt_setprop(blob, nodeoffset,
 202                                                   "linux,initrd-end",
 203                                                   &initrd_end,
 204                                                   sizeof(initrd_end));
 205                                 if (err < 0)
 206                                         puts("error adding linux,initrd-end\n");
 207                         }
 208                 }
 209         }
 210
 211         if (lpae) {
 212                 /*
 213                  * the initrd and other reserved memory areas are
 214                  * embedded in in the DTB itslef. fix up these addresses
 215                  * to 36 bit format
 216                  */
 217                 reserve_start = (u64 *)((char *)blob +
 218                                        fdt_off_mem_rsvmap(blob));
 219                 while (1) {
 220                         *reserve_start = __cpu_to_be64(*reserve_start);
 221                         size = __cpu_to_be64(*(reserve_start + 1));
 222                         if (size) {
 223                                 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
 224                                 *reserve_start +=
 225                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 226                                 *reserve_start =
 227                                         __cpu_to_be64(*reserve_start);
 228                         } else {
 229                                 break;
 230                         }
 231                         reserve_start += 2;
 232                 }
 233         }
 234
 235         ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 236 }
 237 #endif /* CONFIG_OF_BOARD_SETUP */
 238
 239 #if defined(CONFIG_DTB_RESELECT)
 240 int __weak embedded_dtb_select(void)
 241 {
 242         return 0;
 243 }
 244 #endif