2 * Keystone : Board initialization
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
15 #include <asm/arch/ddr3.h>
16 #include <asm/arch/psc_defs.h>
17 #include <asm/ti-common/ti-aemif.h>
18 #include <asm/ti-common/keystone_net.h>
20 DECLARE_GLOBAL_DATA_PTR
;
22 static struct aemif_config aemif_configs
[] = {
24 .mode
= AEMIF_MODE_NAND
,
32 .width
= AEMIF_WIDTH_8
,
40 ddr3_size
= ddr3_init();
42 gd
->ram_size
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
,
43 CONFIG_MAX_RAM_BANK_SIZE
);
44 aemif_init(ARRAY_SIZE(aemif_configs
), aemif_configs
);
45 ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE
, ddr3_size
);
51 gd
->bd
->bi_boot_params
= CONFIG_LINUX_BOOT_PARAM_ADDR
;
56 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
57 int get_eth_env_param(char *env_name
)
62 env
= getenv(env_name
);
64 res
= simple_strtol(env
, NULL
, 0);
69 int board_eth_init(bd_t
*bis
)
74 char link_type_name
[32];
76 /* By default, select PA PLL clock as PA clock source */
77 if (psc_enable_module(KS2_LPSC_PA
))
79 if (psc_enable_module(KS2_LPSC_CPGMAC
))
81 if (psc_enable_module(KS2_LPSC_CRYPTO
))
83 pass_pll_pa_clk_enable();
85 port_num
= get_num_eth_ports();
87 for (j
= 0; j
< port_num
; j
++) {
88 sprintf(link_type_name
, "sgmii%d_link_type", j
);
89 res
= get_eth_env_param(link_type_name
);
91 eth_priv_cfg
[j
].sgmii_link_type
= res
;
93 keystone2_emac_initialize(ð_priv_cfg
[j
]);
100 #ifdef CONFIG_SPL_BUILD
101 void spl_board_init(void)
103 spl_init_keystone_plls();
104 preloader_console_init();
107 u32
spl_boot_device(void)
109 #if defined(CONFIG_SPL_SPI_LOAD)
110 return BOOT_DEVICE_SPI
;
112 puts("Unknown boot device\n");
118 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
119 int ft_board_setup(void *blob
, bd_t
*bd
)
129 int unitrd_fixup
= 0;
131 env
= getenv("mem_lpae");
132 lpae
= env
&& simple_strtol(env
, NULL
, 0);
133 env
= getenv("uinitrd_fixup");
134 unitrd_fixup
= env
&& simple_strtol(env
, NULL
, 0);
138 env
= getenv("ddr3a_size");
140 ddr3a_size
= simple_strtol(env
, NULL
, 10);
141 if ((ddr3a_size
!= 8) && (ddr3a_size
!= 4))
146 start
[0] = bd
->bi_dram
[0].start
;
147 size
[0] = bd
->bi_dram
[0].size
;
149 /* adjust memory start address for LPAE */
151 start
[0] -= CONFIG_SYS_SDRAM_BASE
;
152 start
[0] += CONFIG_SYS_LPAE_SDRAM_BASE
;
155 if ((size
[0] == 0x80000000) && (ddr3a_size
!= 0)) {
156 size
[1] = ((u64
)ddr3a_size
- 2) << 30;
157 start
[1] = 0x880000000;
161 /* reserve memory at start of bank */
162 env
= getenv("mem_reserve_head");
164 start
[0] += ustrtoul(env
, &endp
, 0);
165 size
[0] -= ustrtoul(env
, &endp
, 0);
168 env
= getenv("mem_reserve");
170 size
[0] -= ustrtoul(env
, &endp
, 0);
172 fdt_fixup_memory_banks(blob
, start
, size
, nbanks
);
174 /* Fix up the initrd */
175 if (lpae
&& unitrd_fixup
) {
178 u64 initrd_start
, initrd_end
;
180 nodeoffset
= fdt_path_offset(blob
, "/chosen");
181 if (nodeoffset
>= 0) {
182 prop1
= (u32
*)fdt_getprop(blob
, nodeoffset
,
183 "linux,initrd-start", NULL
);
184 prop2
= (u32
*)fdt_getprop(blob
, nodeoffset
,
185 "linux,initrd-end", NULL
);
186 if (prop1
&& prop2
) {
187 initrd_start
= __be32_to_cpu(*prop1
);
188 initrd_start
-= CONFIG_SYS_SDRAM_BASE
;
189 initrd_start
+= CONFIG_SYS_LPAE_SDRAM_BASE
;
190 initrd_start
= __cpu_to_be64(initrd_start
);
191 initrd_end
= __be32_to_cpu(*prop2
);
192 initrd_end
-= CONFIG_SYS_SDRAM_BASE
;
193 initrd_end
+= CONFIG_SYS_LPAE_SDRAM_BASE
;
194 initrd_end
= __cpu_to_be64(initrd_end
);
196 err
= fdt_delprop(blob
, nodeoffset
,
197 "linux,initrd-start");
199 puts("error deleting initrd-start\n");
201 err
= fdt_delprop(blob
, nodeoffset
,
204 puts("error deleting initrd-end\n");
206 err
= fdt_setprop(blob
, nodeoffset
,
207 "linux,initrd-start",
209 sizeof(initrd_start
));
211 puts("error adding initrd-start\n");
213 err
= fdt_setprop(blob
, nodeoffset
,
218 puts("error adding linux,initrd-end\n");
226 void ft_board_setup_ex(void *blob
, bd_t
*bd
)
233 env
= getenv("mem_lpae");
234 lpae
= env
&& simple_strtol(env
, NULL
, 0);
238 * the initrd and other reserved memory areas are
239 * embedded in in the DTB itslef. fix up these addresses
242 reserve_start
= (u64
*)((char *)blob
+
243 fdt_off_mem_rsvmap(blob
));
245 *reserve_start
= __cpu_to_be64(*reserve_start
);
246 size
= __cpu_to_be64(*(reserve_start
+ 1));
248 *reserve_start
-= CONFIG_SYS_SDRAM_BASE
;
250 CONFIG_SYS_LPAE_SDRAM_BASE
;
252 __cpu_to_be64(*reserve_start
);
260 ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE
);