board/ti/ks2_evm/board_k2e.c

   1 /*
   2  * K2E EVM : Board initialization
   3  *
   4  * (C) Copyright 2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/ddr3.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/ti-common/keystone_net.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 unsigned int get_external_clk(u32 clk)
  18 {
  19         unsigned int clk_freq;
  20
  21         switch (clk) {
  22         case sys_clk:
  23                 clk_freq = 100000000;
  24                 break;
  25         case alt_core_clk:
  26                 clk_freq = 100000000;
  27                 break;
  28         case pa_clk:
  29                 clk_freq = 100000000;
  30                 break;
  31         case ddr3a_clk:
  32                 clk_freq = 100000000;
  33                 break;
  34         default:
  35                 clk_freq = 0;
  36                 break;
  37         }
  38
  39         return clk_freq;
  40 }
  41
  42 static struct pll_init_data core_pll_config[NUM_SPDS] = {
  43         [SPD800]        = CORE_PLL_800,
  44         [SPD850]        = CORE_PLL_850,
  45         [SPD1000]       = CORE_PLL_1000,
  46         [SPD1250]       = CORE_PLL_1250,
  47         [SPD1350]       = CORE_PLL_1350,
  48         [SPD1400]       = CORE_PLL_1400,
  49         [SPD1500]       = CORE_PLL_1500,
  50 };
  51
  52 /* DEV and ARM speed definitions as specified in DEVSPEED register */
  53 int speeds[DEVSPEED_NUMSPDS] = {
  54         SPD850,
  55         SPD1000,
  56         SPD1250,
  57         SPD1350,
  58         SPD1400,
  59         SPD1500,
  60         SPD1400,
  61         SPD1350,
  62         SPD1250,
  63         SPD1000,
  64         SPD850,
  65         SPD800,
  66 };
  67
  68 s16 divn_val[16] = {
  69         0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  70 };
  71
  72 static struct pll_init_data pa_pll_config =
  73         PASS_PLL_1000;
  74
  75 struct pll_init_data *get_pll_init_data(int pll)
  76 {
  77         int speed;
  78         struct pll_init_data *data;
  79
  80         switch (pll) {
  81         case MAIN_PLL:
  82                 speed = get_max_dev_speed(speeds);
  83                 data = &core_pll_config[speed];
  84                 break;
  85         case PASS_PLL:
  86                 data = &pa_pll_config;
  87                 break;
  88         default:
  89                 data = NULL;
  90         }
  91
  92         return data;
  93 }
  94
  95 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  96 struct eth_priv_t eth_priv_cfg[] = {
  97         {
  98                 .int_name        = "K2E_EMAC0",
  99                 .rx_flow         = 0,
 100                 .phy_addr        = 0,
 101                 .slave_port      = 1,
 102                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 103                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 104         },
 105         {
 106                 .int_name        = "K2E_EMAC1",
 107                 .rx_flow         = 8,
 108                 .phy_addr        = 1,
 109                 .slave_port      = 2,
 110                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 111                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 112         },
 113         {
 114                 .int_name        = "K2E_EMAC2",
 115                 .rx_flow         = 16,
 116                 .phy_addr        = 2,
 117                 .slave_port      = 3,
 118                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 119                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 120         },
 121         {
 122                 .int_name        = "K2E_EMAC3",
 123                 .rx_flow         = 24,
 124                 .phy_addr        = 3,
 125                 .slave_port      = 4,
 126                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 127                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 128         },
 129         {
 130                 .int_name        = "K2E_EMAC4",
 131                 .rx_flow         = 32,
 132                 .phy_addr        = 4,
 133                 .slave_port      = 5,
 134                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 135                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 136         },
 137         {
 138                 .int_name        = "K2E_EMAC5",
 139                 .rx_flow         = 40,
 140                 .phy_addr        = 5,
 141                 .slave_port      = 6,
 142                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 143                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 144         },
 145         {
 146                 .int_name        = "K2E_EMAC6",
 147                 .rx_flow         = 48,
 148                 .phy_addr        = 6,
 149                 .slave_port      = 7,
 150                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 151                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 152         },
 153         {
 154                 .int_name        = "K2E_EMAC7",
 155                 .rx_flow         = 56,
 156                 .phy_addr        = 7,
 157                 .slave_port      = 8,
 158                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 159                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 160         },
 161 };
 162
 163 int get_num_eth_ports(void)
 164 {
 165         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 166 }
 167 #endif
 168
 169 #if defined(CONFIG_MULTI_DTB_FIT)
 170 int board_fit_config_name_match(const char *name)
 171 {
 172         if (!strcmp(name, "keystone-k2e-evm"))
 173                 return 0;
 174
 175         return -1;
 176 }
 177 #endif
 178
 179 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 180 int board_early_init_f(void)
 181 {
 182         init_plls();
 183
 184         return 0;
 185 }
 186 #endif
 187
 188 #ifdef CONFIG_SPL_BUILD
 189 void spl_init_keystone_plls(void)
 190 {
 191         init_plls();
 192 }
 193 #endif