board/ti/ks2_evm/board_k2e.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K2E EVM : Board initialization
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/ddr3.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/ti-common/keystone_net.h>
  13
  14 unsigned int get_external_clk(u32 clk)
  15 {
  16         unsigned int clk_freq;
  17
  18         switch (clk) {
  19         case sys_clk:
  20                 clk_freq = 100000000;
  21                 break;
  22         case alt_core_clk:
  23                 clk_freq = 100000000;
  24                 break;
  25         case pa_clk:
  26                 clk_freq = 100000000;
  27                 break;
  28         case ddr3a_clk:
  29                 clk_freq = 100000000;
  30                 break;
  31         default:
  32                 clk_freq = 0;
  33                 break;
  34         }
  35
  36         return clk_freq;
  37 }
  38
  39 static struct pll_init_data core_pll_config[NUM_SPDS] = {
  40         [SPD800]        = CORE_PLL_800,
  41         [SPD850]        = CORE_PLL_850,
  42         [SPD1000]       = CORE_PLL_1000,
  43         [SPD1250]       = CORE_PLL_1250,
  44         [SPD1350]       = CORE_PLL_1350,
  45         [SPD1400]       = CORE_PLL_1400,
  46         [SPD1500]       = CORE_PLL_1500,
  47 };
  48
  49 /* DEV and ARM speed definitions as specified in DEVSPEED register */
  50 int speeds[DEVSPEED_NUMSPDS] = {
  51         SPD850,
  52         SPD1000,
  53         SPD1250,
  54         SPD1350,
  55         SPD1400,
  56         SPD1500,
  57         SPD1400,
  58         SPD1350,
  59         SPD1250,
  60         SPD1000,
  61         SPD850,
  62         SPD800,
  63 };
  64
  65 s16 divn_val[16] = {
  66         0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  67 };
  68
  69 static struct pll_init_data pa_pll_config =
  70         PASS_PLL_1000;
  71
  72 struct pll_init_data *get_pll_init_data(int pll)
  73 {
  74         int speed;
  75         struct pll_init_data *data;
  76
  77         switch (pll) {
  78         case MAIN_PLL:
  79                 speed = get_max_dev_speed(speeds);
  80                 data = &core_pll_config[speed];
  81                 break;
  82         case PASS_PLL:
  83                 data = &pa_pll_config;
  84                 break;
  85         default:
  86                 data = NULL;
  87         }
  88
  89         return data;
  90 }
  91
  92 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
  93 struct eth_priv_t eth_priv_cfg[] = {
  94         {
  95                 .int_name        = "K2E_EMAC0",
  96                 .rx_flow         = 0,
  97                 .phy_addr        = 0,
  98                 .slave_port      = 1,
  99                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 100                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 101         },
 102         {
 103                 .int_name        = "K2E_EMAC1",
 104                 .rx_flow         = 8,
 105                 .phy_addr        = 1,
 106                 .slave_port      = 2,
 107                 .sgmii_link_type = SGMII_LINK_MAC_PHY,
 108                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 109         },
 110         {
 111                 .int_name        = "K2E_EMAC2",
 112                 .rx_flow         = 16,
 113                 .phy_addr        = 2,
 114                 .slave_port      = 3,
 115                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 116                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 117         },
 118         {
 119                 .int_name        = "K2E_EMAC3",
 120                 .rx_flow         = 24,
 121                 .phy_addr        = 3,
 122                 .slave_port      = 4,
 123                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 124                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 125         },
 126         {
 127                 .int_name        = "K2E_EMAC4",
 128                 .rx_flow         = 32,
 129                 .phy_addr        = 4,
 130                 .slave_port      = 5,
 131                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 132                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 133         },
 134         {
 135                 .int_name        = "K2E_EMAC5",
 136                 .rx_flow         = 40,
 137                 .phy_addr        = 5,
 138                 .slave_port      = 6,
 139                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 140                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 141         },
 142         {
 143                 .int_name        = "K2E_EMAC6",
 144                 .rx_flow         = 48,
 145                 .phy_addr        = 6,
 146                 .slave_port      = 7,
 147                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 148                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 149         },
 150         {
 151                 .int_name        = "K2E_EMAC7",
 152                 .rx_flow         = 56,
 153                 .phy_addr        = 7,
 154                 .slave_port      = 8,
 155                 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
 156                 .phy_if          = PHY_INTERFACE_MODE_SGMII,
 157         },
 158 };
 159
 160 int get_num_eth_ports(void)
 161 {
 162         return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
 163 }
 164 #endif
 165
 166 #if defined(CONFIG_MULTI_DTB_FIT)
 167 int board_fit_config_name_match(const char *name)
 168 {
 169         if (!strcmp(name, "keystone-k2e-evm"))
 170                 return 0;
 171
 172         return -1;
 173 }
 174 #endif
 175
 176 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 177 int board_early_init_f(void)
 178 {
 179         init_plls();
 180
 181         return 0;
 182 }
 183 #endif
 184
 185 #ifdef CONFIG_SPL_BUILD
 186 void spl_init_keystone_plls(void)
 187 {
 188         init_plls();
 189 }
 190 #endif